circuit TLSPI :
  module TLSPI :
    input in_clock : Clock
    input reset : UInt<1>
    output auto_int_out_0 : UInt<1>
    output auto_r_in_a_ready : UInt<1>
    input auto_r_in_a_valid : UInt<1>
    input auto_r_in_a_bits_opcode : UInt<3>
    input auto_r_in_a_bits_param : UInt<3>
    input auto_r_in_a_bits_size : UInt<2>
    input auto_r_in_a_bits_source : UInt<7>
    input auto_r_in_a_bits_address : UInt<29>
    input auto_r_in_a_bits_mask : UInt<4>
    input auto_r_in_a_bits_data : UInt<32>
    input auto_r_in_b_ready : UInt<1>
    output auto_r_in_b_valid : UInt<1>
    output auto_r_in_b_bits_opcode : UInt<3>
    output auto_r_in_b_bits_param : UInt<2>
    output auto_r_in_b_bits_size : UInt<2>
    output auto_r_in_b_bits_source : UInt<7>
    output auto_r_in_b_bits_address : UInt<29>
    output auto_r_in_b_bits_mask : UInt<4>
    output auto_r_in_b_bits_data : UInt<32>
    output auto_r_in_c_ready : UInt<1>
    input auto_r_in_c_valid : UInt<1>
    input auto_r_in_c_bits_opcode : UInt<3>
    input auto_r_in_c_bits_param : UInt<3>
    input auto_r_in_c_bits_size : UInt<2>
    input auto_r_in_c_bits_source : UInt<7>
    input auto_r_in_c_bits_address : UInt<29>
    input auto_r_in_c_bits_data : UInt<32>
    input auto_r_in_c_bits_error : UInt<1>
    input auto_r_in_d_ready : UInt<1>
    output auto_r_in_d_valid : UInt<1>
    output auto_r_in_d_bits_opcode : UInt<3>
    output auto_r_in_d_bits_param : UInt<2>
    output auto_r_in_d_bits_size : UInt<2>
    output auto_r_in_d_bits_source : UInt<7>
    output auto_r_in_d_bits_sink : UInt<1>
    output auto_r_in_d_bits_data : UInt<32>
    output auto_r_in_d_bits_error : UInt<1>
    output auto_r_in_e_ready : UInt<1>
    input auto_r_in_e_valid : UInt<1>
    input auto_r_in_e_bits_sink : UInt<1>
    output io_port_sck : UInt<1>
    input io_port_dq_0_i : UInt<1>
    output io_port_dq_0_o : UInt<1>
    output io_port_dq_0_oe : UInt<1>
    input io_port_dq_1_i : UInt<1>
    output io_port_dq_1_o : UInt<1>
    output io_port_dq_1_oe : UInt<1>
    input io_port_dq_2_i : UInt<1>
    output io_port_dq_2_o : UInt<1>
    output io_port_dq_2_oe : UInt<1>
    input io_port_dq_3_i : UInt<1>
    output io_port_dq_3_o : UInt<1>
    output io_port_dq_3_oe : UInt<1>
    output io_port_cs_0 : UInt<1>
    output io_port_cs_1 : UInt<1>
    output io_port_cs_2 : UInt<1>
    output io_port_cs_3 : UInt<1>

    wire TLMonitor_reset : UInt<1>
    wire TLMonitor_io_in_a_ready : UInt<1>
    wire TLMonitor_io_in_a_valid : UInt<1>
    wire TLMonitor_io_in_a_bits_opcode : UInt<3>
    wire TLMonitor_io_in_a_bits_param : UInt<3>
    wire TLMonitor_io_in_a_bits_size : UInt<2>
    wire TLMonitor_io_in_a_bits_source : UInt<7>
    wire TLMonitor_io_in_a_bits_address : UInt<29>
    wire TLMonitor_io_in_a_bits_mask : UInt<4>
    wire TLMonitor_io_in_c_valid : UInt<1>
    wire TLMonitor_io_in_d_ready : UInt<1>
    wire TLMonitor_io_in_d_valid : UInt<1>
    wire TLMonitor_io_in_d_bits_opcode : UInt<3>
    wire TLMonitor_io_in_d_bits_size : UInt<2>
    wire TLMonitor_io_in_d_bits_source : UInt<7>
    wire TLMonitor_io_in_e_valid : UInt<1>
    node TLMonitor__T_42 = dshl(UInt<2>("h3"), TLMonitor_io_in_a_bits_size) @[package.scala 104:77]
    node TLMonitor__T_43 = bits(TLMonitor__T_42, 1, 0) @[package.scala 104:82]
    node TLMonitor__T_44 = not(TLMonitor__T_43) @[package.scala 104:46]
    node TLMonitor__GEN_18 = pad(TLMonitor__T_44, 29) @[Edges.scala 21:16]
    node TLMonitor__T_45 = and(TLMonitor_io_in_a_bits_address, TLMonitor__GEN_18) @[Edges.scala 21:16]
    node TLMonitor__T_47 = eq(TLMonitor__T_45, UInt<29>("h0")) @[Edges.scala 21:24]
    node TLMonitor__T_48 = bits(TLMonitor_io_in_a_bits_size, 0, 0) @[OneHot.scala 49:27]
    node TLMonitor__T_50 = dshl(UInt<1>("h1"), TLMonitor__T_48) @[OneHot.scala 50:12]
    node TLMonitor__T_53 = or(TLMonitor__T_50, UInt<2>("h1")) @[Misc.scala 237:54]
    node TLMonitor__T_55 = geq(TLMonitor_io_in_a_bits_size, UInt<2>("h2")) @[Misc.scala 241:21]
    node TLMonitor__T_57 = bits(TLMonitor__T_53, 1, 1) @[Misc.scala 244:26]
    node TLMonitor__T_58 = bits(TLMonitor_io_in_a_bits_address, 1, 1) @[Misc.scala 245:26]
    node TLMonitor__T_60 = not(TLMonitor__T_58) @[Misc.scala 246:20]
    node TLMonitor__T_62 = and(TLMonitor__T_57, TLMonitor__T_60) @[Misc.scala 250:38]
    node TLMonitor__T_63 = or(TLMonitor__T_55, TLMonitor__T_62) @[Misc.scala 250:29]
    node TLMonitor__T_65 = and(TLMonitor__T_57, TLMonitor__T_58) @[Misc.scala 250:38]
    node TLMonitor__T_66 = or(TLMonitor__T_55, TLMonitor__T_65) @[Misc.scala 250:29]
    node TLMonitor__T_67 = bits(TLMonitor__T_53, 0, 0) @[Misc.scala 244:26]
    node TLMonitor__T_68 = bits(TLMonitor_io_in_a_bits_address, 0, 0) @[Misc.scala 245:26]
    node TLMonitor__T_70 = not(TLMonitor__T_68) @[Misc.scala 246:20]
    node TLMonitor__T_71 = and(TLMonitor__T_60, TLMonitor__T_70) @[Misc.scala 249:27]
    node TLMonitor__T_72 = and(TLMonitor__T_67, TLMonitor__T_71) @[Misc.scala 250:38]
    node TLMonitor__T_73 = or(TLMonitor__T_63, TLMonitor__T_72) @[Misc.scala 250:29]
    node TLMonitor__T_74 = and(TLMonitor__T_60, TLMonitor__T_68) @[Misc.scala 249:27]
    node TLMonitor__T_75 = and(TLMonitor__T_67, TLMonitor__T_74) @[Misc.scala 250:38]
    node TLMonitor__T_76 = or(TLMonitor__T_63, TLMonitor__T_75) @[Misc.scala 250:29]
    node TLMonitor__T_77 = and(TLMonitor__T_58, TLMonitor__T_70) @[Misc.scala 249:27]
    node TLMonitor__T_78 = and(TLMonitor__T_67, TLMonitor__T_77) @[Misc.scala 250:38]
    node TLMonitor__T_79 = or(TLMonitor__T_66, TLMonitor__T_78) @[Misc.scala 250:29]
    node TLMonitor__T_80 = and(TLMonitor__T_58, TLMonitor__T_68) @[Misc.scala 249:27]
    node TLMonitor__T_81 = and(TLMonitor__T_67, TLMonitor__T_80) @[Misc.scala 250:38]
    node TLMonitor__T_82 = or(TLMonitor__T_66, TLMonitor__T_81) @[Misc.scala 250:29]
    node TLMonitor__T_83 = cat(TLMonitor__T_76, TLMonitor__T_73) @[Cat.scala 30:58]
    node TLMonitor__T_84 = cat(TLMonitor__T_82, TLMonitor__T_79) @[Cat.scala 30:58]
    node TLMonitor__T_85 = cat(TLMonitor__T_84, TLMonitor__T_83) @[Cat.scala 30:58]
    node TLMonitor__T_87 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h6")) @[Monitor.scala 40:25]
    node TLMonitor__T_92 = xor(TLMonitor_io_in_a_bits_address, UInt<29>("h10024000")) @[Parameters.scala 119:31]
    node TLMonitor__T_93 = cvt(TLMonitor__T_92) @[Parameters.scala 119:49]
    node TLMonitor__T_95 = and(TLMonitor__T_93, SInt<30>("h-1000")) @[Parameters.scala 119:52]
    node TLMonitor__T_96 = asSInt(TLMonitor__T_95) @[Parameters.scala 119:52]
    node TLMonitor__T_98 = eq(TLMonitor__T_96, SInt<30>("h0")) @[Parameters.scala 119:67]
    node TLMonitor__T_105 = not(TLMonitor_reset) @[Monitor.scala 41:14]
    node TLMonitor__T_118 = or(TLMonitor__T_55, TLMonitor_reset) @[Monitor.scala 44:14]
    node TLMonitor__T_120 = not(TLMonitor__T_118) @[Monitor.scala 44:14]
    node TLMonitor__T_122 = or(TLMonitor__T_47, TLMonitor_reset) @[Monitor.scala 45:14]
    node TLMonitor__T_124 = not(TLMonitor__T_122) @[Monitor.scala 45:14]
    node TLMonitor__T_126 = leq(TLMonitor_io_in_a_bits_param, UInt<3>("h2")) @[Bundles.scala 71:27]
    node TLMonitor__T_128 = or(TLMonitor__T_126, TLMonitor_reset) @[Monitor.scala 46:14]
    node TLMonitor__T_130 = not(TLMonitor__T_128) @[Monitor.scala 46:14]
    node TLMonitor__T_131 = not(TLMonitor_io_in_a_bits_mask) @[Monitor.scala 47:15]
    node TLMonitor__T_133 = eq(TLMonitor__T_131, UInt<4>("h0")) @[Monitor.scala 47:28]
    node TLMonitor__T_135 = or(TLMonitor__T_133, TLMonitor_reset) @[Monitor.scala 47:14]
    node TLMonitor__T_137 = not(TLMonitor__T_135) @[Monitor.scala 47:14]
    node TLMonitor__T_139 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h7")) @[Monitor.scala 50:25]
    node TLMonitor__T_184 = neq(TLMonitor_io_in_a_bits_param, UInt<3>("h0")) @[Monitor.scala 57:28]
    node TLMonitor__T_186 = or(TLMonitor__T_184, TLMonitor_reset) @[Monitor.scala 57:14]
    node TLMonitor__T_188 = not(TLMonitor__T_186) @[Monitor.scala 57:14]
    node TLMonitor__T_197 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h4")) @[Monitor.scala 61:25]
    node TLMonitor__T_202 = leq(TLMonitor_io_in_a_bits_size, UInt<2>("h2")) @[Parameters.scala 88:42]
    node TLMonitor__T_213 = and(TLMonitor__T_202, TLMonitor__T_98) @[Parameters.scala 157:56]
    node TLMonitor__T_217 = or(TLMonitor__T_213, TLMonitor_reset) @[Monitor.scala 62:14]
    node TLMonitor__T_219 = not(TLMonitor__T_217) @[Monitor.scala 62:14]
    node TLMonitor__T_229 = eq(TLMonitor_io_in_a_bits_param, UInt<3>("h0")) @[Monitor.scala 65:28]
    node TLMonitor__T_231 = or(TLMonitor__T_229, TLMonitor_reset) @[Monitor.scala 65:14]
    node TLMonitor__T_233 = not(TLMonitor__T_231) @[Monitor.scala 65:14]
    node TLMonitor__T_234 = eq(TLMonitor_io_in_a_bits_mask, TLMonitor__T_85) @[Monitor.scala 66:27]
    node TLMonitor__T_236 = or(TLMonitor__T_234, TLMonitor_reset) @[Monitor.scala 66:14]
    node TLMonitor__T_238 = not(TLMonitor__T_236) @[Monitor.scala 66:14]
    node TLMonitor__T_240 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h0")) @[Monitor.scala 69:25]
    node TLMonitor__T_283 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h1")) @[Monitor.scala 77:25]
    node TLMonitor__T_320 = not(TLMonitor__T_85) @[Monitor.scala 82:30]
    node TLMonitor__T_321 = and(TLMonitor_io_in_a_bits_mask, TLMonitor__T_320) @[Monitor.scala 82:28]
    node TLMonitor__T_323 = eq(TLMonitor__T_321, UInt<4>("h0")) @[Monitor.scala 82:37]
    node TLMonitor__T_325 = or(TLMonitor__T_323, TLMonitor_reset) @[Monitor.scala 82:14]
    node TLMonitor__T_327 = not(TLMonitor__T_325) @[Monitor.scala 82:14]
    node TLMonitor__T_329 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h2")) @[Monitor.scala 85:25]
    node TLMonitor__T_357 = leq(TLMonitor_io_in_a_bits_param, UInt<3>("h4")) @[Bundles.scala 96:33]
    node TLMonitor__T_359 = or(TLMonitor__T_357, TLMonitor_reset) @[Monitor.scala 89:14]
    node TLMonitor__T_361 = not(TLMonitor__T_359) @[Monitor.scala 89:14]
    node TLMonitor__T_368 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h3")) @[Monitor.scala 93:25]
    node TLMonitor__T_396 = leq(TLMonitor_io_in_a_bits_param, UInt<3>("h3")) @[Bundles.scala 103:30]
    node TLMonitor__T_398 = or(TLMonitor__T_396, TLMonitor_reset) @[Monitor.scala 97:14]
    node TLMonitor__T_400 = not(TLMonitor__T_398) @[Monitor.scala 97:14]
    node TLMonitor__T_407 = eq(TLMonitor_io_in_a_bits_opcode, UInt<3>("h5")) @[Monitor.scala 101:25]
    node TLMonitor__T_440 = leq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h6")) @[Bundles.scala 43:24]
    node TLMonitor__T_442 = or(TLMonitor__T_440, TLMonitor_reset) @[Monitor.scala 247:12]
    node TLMonitor__T_444 = not(TLMonitor__T_442) @[Monitor.scala 247:12]
    node TLMonitor__T_468 = eq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h6")) @[Monitor.scala 252:25]
    node TLMonitor__T_478 = geq(TLMonitor_io_in_d_bits_size, UInt<2>("h2")) @[Monitor.scala 255:27]
    node TLMonitor__T_480 = or(TLMonitor__T_478, TLMonitor_reset) @[Monitor.scala 255:14]
    node TLMonitor__T_482 = not(TLMonitor__T_480) @[Monitor.scala 255:14]
    node TLMonitor__T_490 = eq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h4")) @[Monitor.scala 259:25]
    node TLMonitor__T_512 = eq(TLMonitor_io_in_d_bits_opcode, UInt<3>("h5")) @[Monitor.scala 266:25]
    node TLMonitor__T_588 = not(TLMonitor_io_in_c_valid) @[Monitor.scala 309:15]
    node TLMonitor__T_590 = or(TLMonitor__T_588, TLMonitor_reset) @[Monitor.scala 309:14]
    node TLMonitor__T_592 = not(TLMonitor__T_590) @[Monitor.scala 309:14]
    node TLMonitor__T_594 = not(TLMonitor_io_in_e_valid) @[Monitor.scala 310:15]
    node TLMonitor__T_596 = or(TLMonitor__T_594, TLMonitor_reset) @[Monitor.scala 310:14]
    node TLMonitor__T_598 = not(TLMonitor__T_596) @[Monitor.scala 310:14]
    node TLMonitor__T_599 = and(TLMonitor_io_in_a_ready, TLMonitor_io_in_a_valid) @[Bundles.scala 207:36]
    reg TLMonitor__T_613 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_613) @[Edges.scala 220:27]
    node TLMonitor__T_615 = sub(TLMonitor__T_613, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_617 = tail(TLMonitor__T_615, 1) @[Edges.scala 221:28]
    node TLMonitor__T_619 = not(TLMonitor__T_613) @[Edges.scala 222:25]
    node TLMonitor__T_628 = mux(TLMonitor__T_619, UInt<1>("h0"), TLMonitor__T_617) @[Edges.scala 227:21]
    node TLMonitor__GEN_0 = mux(TLMonitor__T_599, TLMonitor__T_628, TLMonitor__T_613) @[Edges.scala 226:17 227:15 220:27]
    reg TLMonitor__T_630 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_630) @[Monitor.scala 316:22]
    reg TLMonitor__T_632 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_632) @[Monitor.scala 317:22]
    reg TLMonitor__T_634 : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_634) @[Monitor.scala 318:22]
    reg TLMonitor__T_636 : UInt<7>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_636) @[Monitor.scala 319:22]
    reg TLMonitor__T_638 : UInt<29>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_638) @[Monitor.scala 320:22]
    node TLMonitor__T_640 = not(TLMonitor__T_619) @[Monitor.scala 321:22]
    node TLMonitor__T_641 = and(TLMonitor_io_in_a_valid, TLMonitor__T_640) @[Monitor.scala 321:19]
    node TLMonitor__T_642 = eq(TLMonitor_io_in_a_bits_opcode, TLMonitor__T_630) @[Monitor.scala 322:29]
    node TLMonitor__T_644 = or(TLMonitor__T_642, TLMonitor_reset) @[Monitor.scala 322:14]
    node TLMonitor__T_646 = not(TLMonitor__T_644) @[Monitor.scala 322:14]
    node TLMonitor__T_647 = eq(TLMonitor_io_in_a_bits_param, TLMonitor__T_632) @[Monitor.scala 323:29]
    node TLMonitor__T_649 = or(TLMonitor__T_647, TLMonitor_reset) @[Monitor.scala 323:14]
    node TLMonitor__T_651 = not(TLMonitor__T_649) @[Monitor.scala 323:14]
    node TLMonitor__T_652 = eq(TLMonitor_io_in_a_bits_size, TLMonitor__T_634) @[Monitor.scala 324:29]
    node TLMonitor__T_654 = or(TLMonitor__T_652, TLMonitor_reset) @[Monitor.scala 324:14]
    node TLMonitor__T_656 = not(TLMonitor__T_654) @[Monitor.scala 324:14]
    node TLMonitor__T_657 = eq(TLMonitor_io_in_a_bits_source, TLMonitor__T_636) @[Monitor.scala 325:29]
    node TLMonitor__T_659 = or(TLMonitor__T_657, TLMonitor_reset) @[Monitor.scala 325:14]
    node TLMonitor__T_661 = not(TLMonitor__T_659) @[Monitor.scala 325:14]
    node TLMonitor__T_662 = eq(TLMonitor_io_in_a_bits_address, TLMonitor__T_638) @[Monitor.scala 326:29]
    node TLMonitor__T_664 = or(TLMonitor__T_662, TLMonitor_reset) @[Monitor.scala 326:14]
    node TLMonitor__T_666 = not(TLMonitor__T_664) @[Monitor.scala 326:14]
    node TLMonitor__T_668 = and(TLMonitor__T_599, TLMonitor__T_619) @[Monitor.scala 328:20]
    node TLMonitor__T_669 = and(TLMonitor_io_in_d_ready, TLMonitor_io_in_d_valid) @[Bundles.scala 207:36]
    reg TLMonitor__T_681 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_681) @[Edges.scala 220:27]
    node TLMonitor__T_683 = sub(TLMonitor__T_681, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_685 = tail(TLMonitor__T_683, 1) @[Edges.scala 221:28]
    node TLMonitor__T_687 = not(TLMonitor__T_681) @[Edges.scala 222:25]
    node TLMonitor__T_696 = mux(TLMonitor__T_687, UInt<1>("h0"), TLMonitor__T_685) @[Edges.scala 227:21]
    node TLMonitor__GEN_6 = mux(TLMonitor__T_669, TLMonitor__T_696, TLMonitor__T_681) @[Edges.scala 226:17 227:15 220:27]
    reg TLMonitor__T_698 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_698) @[Monitor.scala 387:22]
    reg TLMonitor__T_702 : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_702) @[Monitor.scala 389:22]
    reg TLMonitor__T_704 : UInt<7>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_704) @[Monitor.scala 390:22]
    node TLMonitor__T_711 = not(TLMonitor__T_687) @[Monitor.scala 393:22]
    node TLMonitor__T_712 = and(TLMonitor_io_in_d_valid, TLMonitor__T_711) @[Monitor.scala 393:19]
    node TLMonitor__T_713 = eq(TLMonitor_io_in_d_bits_opcode, TLMonitor__T_698) @[Monitor.scala 394:29]
    node TLMonitor__T_715 = or(TLMonitor__T_713, TLMonitor_reset) @[Monitor.scala 394:14]
    node TLMonitor__T_717 = not(TLMonitor__T_715) @[Monitor.scala 394:14]
    node TLMonitor__T_723 = eq(TLMonitor_io_in_d_bits_size, TLMonitor__T_702) @[Monitor.scala 396:29]
    node TLMonitor__T_725 = or(TLMonitor__T_723, TLMonitor_reset) @[Monitor.scala 396:14]
    node TLMonitor__T_727 = not(TLMonitor__T_725) @[Monitor.scala 396:14]
    node TLMonitor__T_728 = eq(TLMonitor_io_in_d_bits_source, TLMonitor__T_704) @[Monitor.scala 397:29]
    node TLMonitor__T_730 = or(TLMonitor__T_728, TLMonitor_reset) @[Monitor.scala 397:14]
    node TLMonitor__T_732 = not(TLMonitor__T_730) @[Monitor.scala 397:14]
    node TLMonitor__T_746 = and(TLMonitor__T_669, TLMonitor__T_687) @[Monitor.scala 401:20]
    reg TLMonitor__T_749 : UInt<128>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_749) @[Monitor.scala 420:27]
    reg TLMonitor__T_764 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_764) @[Edges.scala 220:27]
    node TLMonitor__T_766 = sub(TLMonitor__T_764, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_768 = tail(TLMonitor__T_766, 1) @[Edges.scala 221:28]
    node TLMonitor__T_770 = not(TLMonitor__T_764) @[Edges.scala 222:25]
    node TLMonitor__T_779 = mux(TLMonitor__T_770, UInt<1>("h0"), TLMonitor__T_768) @[Edges.scala 227:21]
    node TLMonitor__GEN_13 = mux(TLMonitor__T_599, TLMonitor__T_779, TLMonitor__T_764) @[Edges.scala 226:17 227:15 220:27]
    reg TLMonitor__T_792 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), TLMonitor__T_792) @[Edges.scala 220:27]
    node TLMonitor__T_794 = sub(TLMonitor__T_792, UInt<1>("h1")) @[Edges.scala 221:28]
    node TLMonitor__T_796 = tail(TLMonitor__T_794, 1) @[Edges.scala 221:28]
    node TLMonitor__T_798 = not(TLMonitor__T_792) @[Edges.scala 222:25]
    node TLMonitor__T_807 = mux(TLMonitor__T_798, UInt<1>("h0"), TLMonitor__T_796) @[Edges.scala 227:21]
    node TLMonitor__GEN_14 = mux(TLMonitor__T_669, TLMonitor__T_807, TLMonitor__T_792) @[Edges.scala 226:17 227:15 220:27]
    node TLMonitor__T_812 = and(TLMonitor__T_599, TLMonitor__T_770) @[Monitor.scala 426:27]
    node TLMonitor__T_816 = dshl(UInt<1>("h1"), TLMonitor_io_in_a_bits_source) @[OneHot.scala 45:35]
    node TLMonitor__T_817 = dshr(TLMonitor__T_749, TLMonitor_io_in_a_bits_source) @[Monitor.scala 428:23]
    node TLMonitor__T_818 = bits(TLMonitor__T_817, 0, 0) @[Monitor.scala 428:23]
    node TLMonitor__T_820 = not(TLMonitor__T_818) @[Monitor.scala 428:14]
    node TLMonitor__T_822 = or(TLMonitor__T_820, TLMonitor_reset) @[Monitor.scala 428:13]
    node TLMonitor__T_824 = not(TLMonitor__T_822) @[Monitor.scala 428:13]
    node TLMonitor__GEN_15 = mux(TLMonitor__T_812, TLMonitor__T_816, UInt<128>("h0")) @[Monitor.scala 426:72 427:13]
    node TLMonitor__T_831 = and(TLMonitor__T_669, TLMonitor__T_798) @[Monitor.scala 433:27]
    node TLMonitor__T_835 = not(TLMonitor__T_468) @[Monitor.scala 433:75]
    node TLMonitor__T_836 = and(TLMonitor__T_831, TLMonitor__T_835) @[Monitor.scala 433:72]
    node TLMonitor__T_838 = dshl(UInt<1>("h1"), TLMonitor_io_in_d_bits_source) @[OneHot.scala 45:35]
    node TLMonitor__T_839 = or(TLMonitor__GEN_15, TLMonitor__T_749) @[Monitor.scala 435:21]
    node TLMonitor__T_840 = dshr(TLMonitor__T_839, TLMonitor_io_in_d_bits_source) @[Monitor.scala 435:32]
    node TLMonitor__T_841 = bits(TLMonitor__T_840, 0, 0) @[Monitor.scala 435:32]
    node TLMonitor__T_843 = or(TLMonitor__T_841, TLMonitor_reset) @[Monitor.scala 435:13]
    node TLMonitor__T_845 = not(TLMonitor__T_843) @[Monitor.scala 435:13]
    node TLMonitor__GEN_16 = mux(TLMonitor__T_836, TLMonitor__T_838, UInt<128>("h0")) @[Monitor.scala 433:91 434:13]
    node TLMonitor__T_846 = or(TLMonitor__T_749, TLMonitor__GEN_15) @[Monitor.scala 442:27]
    node TLMonitor__T_847 = not(TLMonitor__GEN_16) @[Monitor.scala 442:38]
    node TLMonitor__T_848 = and(TLMonitor__T_846, TLMonitor__T_847) @[Monitor.scala 442:36]
    node TLMonitor__GEN_19 = and(TLMonitor_io_in_a_valid, TLMonitor__T_87) @[Monitor.scala 41:14]
    node TLMonitor__GEN_31 = and(TLMonitor_io_in_a_valid, TLMonitor__T_139) @[Monitor.scala 51:14]
    node TLMonitor__GEN_45 = and(TLMonitor_io_in_a_valid, TLMonitor__T_197) @[Monitor.scala 62:14]
    node TLMonitor__GEN_53 = and(TLMonitor_io_in_a_valid, TLMonitor__T_240) @[Monitor.scala 70:14]
    node TLMonitor__GEN_61 = and(TLMonitor_io_in_a_valid, TLMonitor__T_283) @[Monitor.scala 78:14]
    node TLMonitor__GEN_69 = and(TLMonitor_io_in_a_valid, TLMonitor__T_329) @[Monitor.scala 86:14]
    node TLMonitor__GEN_77 = and(TLMonitor_io_in_a_valid, TLMonitor__T_368) @[Monitor.scala 94:14]
    node TLMonitor__GEN_85 = and(TLMonitor_io_in_a_valid, TLMonitor__T_407) @[Monitor.scala 102:14]
    node TLMonitor__GEN_91 = and(TLMonitor_io_in_d_valid, TLMonitor__T_468) @[Monitor.scala 255:14]
    node TLMonitor__GEN_93 = and(TLMonitor_io_in_d_valid, TLMonitor__T_490) @[Monitor.scala 262:14]
    node TLMonitor__GEN_95 = and(TLMonitor_io_in_d_valid, TLMonitor__T_512) @[Monitor.scala 269:14]
    TLMonitor__T_613 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_0) @[Edges.scala 220:{27,27}]
    TLMonitor__T_630 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_opcode, TLMonitor__T_630) @[Monitor.scala 328:32 329:15 316:22]
    TLMonitor__T_632 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_param, TLMonitor__T_632) @[Monitor.scala 328:32 330:15 317:22]
    TLMonitor__T_634 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_size, TLMonitor__T_634) @[Monitor.scala 328:32 331:15 318:22]
    TLMonitor__T_636 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_source, TLMonitor__T_636) @[Monitor.scala 328:32 332:15 319:22]
    TLMonitor__T_638 <= mux(TLMonitor__T_668, TLMonitor_io_in_a_bits_address, TLMonitor__T_638) @[Monitor.scala 328:32 333:15 320:22]
    TLMonitor__T_681 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_6) @[Edges.scala 220:{27,27}]
    TLMonitor__T_698 <= mux(TLMonitor__T_746, TLMonitor_io_in_d_bits_opcode, TLMonitor__T_698) @[Monitor.scala 401:32 402:15 387:22]
    TLMonitor__T_702 <= mux(TLMonitor__T_746, TLMonitor_io_in_d_bits_size, TLMonitor__T_702) @[Monitor.scala 401:32 404:15 389:22]
    TLMonitor__T_704 <= mux(TLMonitor__T_746, TLMonitor_io_in_d_bits_source, TLMonitor__T_704) @[Monitor.scala 401:32 405:15 390:22]
    TLMonitor__T_749 <= mux(TLMonitor_reset, UInt<128>("h0"), TLMonitor__T_848) @[Monitor.scala 420:{27,27} 442:14]
    TLMonitor__T_764 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_13) @[Edges.scala 220:{27,27}]
    TLMonitor__T_792 <= mux(TLMonitor_reset, UInt<1>("h0"), TLMonitor__GEN_14) @[Edges.scala 220:{27,27}]

    wire fifo_reset : UInt<1>
    wire fifo_io_ctrl_fmt_proto : UInt<2>
    wire fifo_io_ctrl_fmt_endian : UInt<1>
    wire fifo_io_ctrl_fmt_iodir : UInt<1>
    wire fifo_io_ctrl_fmt_len : UInt<4>
    wire fifo_io_ctrl_cs_mode : UInt<2>
    wire fifo_io_ctrl_wm_tx : UInt<4>
    wire fifo_io_ctrl_wm_rx : UInt<4>
    wire fifo_io_link_tx_ready : UInt<1>
    wire fifo_io_link_tx_valid : UInt<1>
    wire fifo_io_link_tx_bits : UInt<8>
    wire fifo_io_link_rx_valid : UInt<1>
    wire fifo_io_link_rx_bits : UInt<8>
    wire fifo_io_link_cnt : UInt<8>
    wire fifo_io_link_fmt_proto : UInt<2>
    wire fifo_io_link_fmt_endian : UInt<1>
    wire fifo_io_link_fmt_iodir : UInt<1>
    wire fifo_io_link_cs_set : UInt<1>
    wire fifo_io_link_cs_clear : UInt<1>
    wire fifo_io_tx_ready : UInt<1>
    wire fifo_io_tx_valid : UInt<1>
    wire fifo_io_tx_bits : UInt<8>
    wire fifo_io_rx_ready : UInt<1>
    wire fifo_io_rx_valid : UInt<1>
    wire fifo_io_rx_bits : UInt<8>
    wire fifo_io_ip_txwm : UInt<1>
    wire fifo_io_ip_rxwm : UInt<1>
    wire fifo_txq_reset : UInt<1>
    wire fifo_txq_io_enq_ready : UInt<1>
    wire fifo_txq_io_enq_valid : UInt<1>
    wire fifo_txq_io_enq_bits : UInt<8>
    wire fifo_txq_io_deq_ready : UInt<1>
    wire fifo_txq_io_deq_valid : UInt<1>
    wire fifo_txq_io_deq_bits : UInt<8>
    wire fifo_txq_io_count : UInt<4>
    input fifo_txq_ram_T_63data : UInt<8>
    output fifo_txq_ram_T_63addr : UInt<3>
    output fifo_txq_ram_T_63en : UInt<1>
    output fifo_txq_ram_T_49addr : UInt<3>
    output fifo_txq_ram_T_49en : UInt<1>
    output fifo_txq_ram_T_49data : UInt<8>
    output fifo_txq_ram_T_49mask : UInt<1>
    mem fifo_txq_ram : @[Decoupled.scala 214:24]
      data-type => UInt<8>
      depth => 8
      read-latency => 0
      write-latency => 1
      reader => _T_63
      writer => _T_49
      read-under-write => undefined
    reg fifo_txq_value : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), fifo_txq_value) @[Counter.scala 26:33]
    reg fifo_txq_value_1 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), fifo_txq_value_1) @[Counter.scala 26:33]
    reg fifo_txq_maybe_full : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), fifo_txq_maybe_full) @[Decoupled.scala 217:35]
    node fifo_txq__T_41 = eq(fifo_txq_value, fifo_txq_value_1) @[Decoupled.scala 219:41]
    node fifo_txq__T_43 = not(fifo_txq_maybe_full) @[Decoupled.scala 220:36]
    node fifo_txq_empty = and(fifo_txq__T_41, fifo_txq__T_43) @[Decoupled.scala 220:33]
    node fifo_txq__T_44 = and(fifo_txq__T_41, fifo_txq_maybe_full) @[Decoupled.scala 221:32]
    node fifo_txq_do_enq = and(fifo_txq_io_enq_ready, fifo_txq_io_enq_valid) @[Decoupled.scala 37:37]
    node fifo_txq_do_deq = and(fifo_txq_io_deq_ready, fifo_txq_io_deq_valid) @[Decoupled.scala 37:37]
    node fifo_txq__T_52 = add(fifo_txq_value, UInt<3>("h1")) @[Counter.scala 35:22]
    node fifo_txq__T_53 = tail(fifo_txq__T_52, 1) @[Counter.scala 35:22]
    node fifo_txq__GEN_5 = mux(fifo_txq_do_enq, fifo_txq__T_53, fifo_txq_value) @[Decoupled.scala 225:17 Counter.scala 35:13 26:33]
    node fifo_txq__T_56 = add(fifo_txq_value_1, UInt<3>("h1")) @[Counter.scala 35:22]
    node fifo_txq__T_57 = tail(fifo_txq__T_56, 1) @[Counter.scala 35:22]
    node fifo_txq__GEN_6 = mux(fifo_txq_do_deq, fifo_txq__T_57, fifo_txq_value_1) @[Decoupled.scala 229:17 Counter.scala 35:13 26:33]
    node fifo_txq__T_58 = neq(fifo_txq_do_enq, fifo_txq_do_deq) @[Decoupled.scala 232:16]
    node fifo_txq__GEN_7 = mux(fifo_txq__T_58, fifo_txq_do_enq, fifo_txq_maybe_full) @[Decoupled.scala 232:28 233:16 217:35]
    node fifo_txq__T_64 = sub(fifo_txq_value, fifo_txq_value_1) @[Decoupled.scala 253:40]
    node fifo_txq__T_66 = tail(fifo_txq__T_64, 1) @[Decoupled.scala 253:40]
    node fifo_txq__T_67 = and(fifo_txq_maybe_full, fifo_txq__T_41) @[Decoupled.scala 255:32]
    fifo_txq_io_enq_ready <= not(fifo_txq__T_44) @[Decoupled.scala 237:19]
    fifo_txq_io_deq_valid <= not(fifo_txq_empty) @[Decoupled.scala 236:19]
    fifo_txq_io_deq_bits <= fifo_txq_ram_T_63data @[Decoupled.scala 238:15]
    fifo_txq_io_count <= cat(fifo_txq__T_67, fifo_txq__T_66) @[Cat.scala 30:58]
    fifo_txq_ram_T_63addr <= fifo_txq_value_1 @[Decoupled.scala 238:21]
    fifo_txq_ram_T_63en <= UInt<1>("h1") @[Decoupled.scala 238:21]
    fifo_txq_ram_T_49addr <= fifo_txq_value @[Decoupled.scala 225:17 226:8]
    fifo_txq_ram_T_49en <= and(fifo_txq_io_enq_ready, fifo_txq_io_enq_valid) @[Decoupled.scala 37:37]
    fifo_txq_ram_T_49data <= fifo_txq_io_enq_bits @[Decoupled.scala 225:17 226:24]
    fifo_txq_ram_T_49mask <= UInt<1>("h1") @[Decoupled.scala 225:17 226:24]
    fifo_txq_value <= mux(fifo_txq_reset, UInt<3>("h0"), fifo_txq__GEN_5) @[Counter.scala 26:{33,33}]
    fifo_txq_value_1 <= mux(fifo_txq_reset, UInt<3>("h0"), fifo_txq__GEN_6) @[Counter.scala 26:{33,33}]
    fifo_txq_maybe_full <= mux(fifo_txq_reset, UInt<1>("h0"), fifo_txq__GEN_7) @[Decoupled.scala 217:{35,35}]
    wire fifo_rxq_reset : UInt<1>
    wire fifo_rxq_io_enq_ready : UInt<1>
    wire fifo_rxq_io_enq_valid : UInt<1>
    wire fifo_rxq_io_enq_bits : UInt<8>
    wire fifo_rxq_io_deq_ready : UInt<1>
    wire fifo_rxq_io_deq_valid : UInt<1>
    wire fifo_rxq_io_deq_bits : UInt<8>
    wire fifo_rxq_io_count : UInt<4>
    input fifo_rxq_ram_T_63data : UInt<8>
    output fifo_rxq_ram_T_63addr : UInt<3>
    output fifo_rxq_ram_T_63en : UInt<1>
    output fifo_rxq_ram_T_49addr : UInt<3>
    output fifo_rxq_ram_T_49en : UInt<1>
    output fifo_rxq_ram_T_49data : UInt<3>
    output fifo_rxq_ram_T_49mask : UInt<1>
    mem fifo_rxq_ram : @[Decoupled.scala 214:24]
      data-type => UInt<8>
      depth => 8
      read-latency => 0
      write-latency => 1
      reader => _T_63
      writer => _T_49
      read-under-write => undefined
    reg fifo_rxq_value : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), fifo_rxq_value) @[Counter.scala 26:33]
    reg fifo_rxq_value_1 : UInt<3>, in_clock with :
      reset => (UInt<1>("h0"), fifo_rxq_value_1) @[Counter.scala 26:33]
    reg fifo_rxq_maybe_full : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), fifo_rxq_maybe_full) @[Decoupled.scala 217:35]
    node fifo_rxq__T_41 = eq(fifo_rxq_value, fifo_rxq_value_1) @[Decoupled.scala 219:41]
    node fifo_rxq__T_43 = not(fifo_rxq_maybe_full) @[Decoupled.scala 220:36]
    node fifo_rxq_empty = and(fifo_rxq__T_41, fifo_rxq__T_43) @[Decoupled.scala 220:33]
    node fifo_rxq__T_44 = and(fifo_rxq__T_41, fifo_rxq_maybe_full) @[Decoupled.scala 221:32]
    node fifo_rxq_do_enq = and(fifo_rxq_io_enq_ready, fifo_rxq_io_enq_valid) @[Decoupled.scala 37:37]
    node fifo_rxq_do_deq = and(fifo_rxq_io_deq_ready, fifo_rxq_io_deq_valid) @[Decoupled.scala 37:37]
    node fifo_rxq__T_52 = add(fifo_rxq_value, UInt<3>("h1")) @[Counter.scala 35:22]
    node fifo_rxq__T_53 = tail(fifo_rxq__T_52, 1) @[Counter.scala 35:22]
    node fifo_rxq__GEN_5 = mux(fifo_rxq_do_enq, fifo_rxq__T_53, fifo_rxq_value) @[Decoupled.scala 225:17 Counter.scala 35:13 26:33]
    node fifo_rxq__T_56 = add(fifo_rxq_value_1, UInt<3>("h1")) @[Counter.scala 35:22]
    node fifo_rxq__T_57 = tail(fifo_rxq__T_56, 1) @[Counter.scala 35:22]
    node fifo_rxq__GEN_6 = mux(fifo_rxq_do_deq, fifo_rxq__T_57, fifo_rxq_value_1) @[Decoupled.scala 229:17 Counter.scala 35:13 26:33]
    node fifo_rxq__T_58 = neq(fifo_rxq_do_enq, fifo_rxq_do_deq) @[Decoupled.scala 232:16]
    node fifo_rxq__GEN_7 = mux(fifo_rxq__T_58, fifo_rxq_do_enq, fifo_rxq_maybe_full) @[Decoupled.scala 232:28 233:16 217:35]
    node fifo_rxq__T_64 = sub(fifo_rxq_value, fifo_rxq_value_1) @[Decoupled.scala 253:40]
    node fifo_rxq__T_66 = tail(fifo_rxq__T_64, 1) @[Decoupled.scala 253:40]
    node fifo_rxq__T_67 = and(fifo_rxq_maybe_full, fifo_rxq__T_41) @[Decoupled.scala 255:32]
    fifo_rxq_io_enq_ready <= not(fifo_rxq__T_44) @[Decoupled.scala 237:19]
    fifo_rxq_io_deq_valid <= not(fifo_rxq_empty) @[Decoupled.scala 236:19]
    fifo_rxq_io_deq_bits <= fifo_rxq_ram_T_63data @[Decoupled.scala 238:15]
    fifo_rxq_io_count <= cat(fifo_rxq__T_67, fifo_rxq__T_66) @[Cat.scala 30:58]
    fifo_rxq_ram_T_63addr <= fifo_rxq_value_1 @[Decoupled.scala 238:21]
    fifo_rxq_ram_T_63en <= UInt<1>("h1") @[Decoupled.scala 238:21]
    fifo_rxq_ram_T_49addr <= fifo_rxq_value @[Decoupled.scala 225:17 226:8]
    fifo_rxq_ram_T_49en <= and(fifo_rxq_io_enq_ready, fifo_rxq_io_enq_valid) @[Decoupled.scala 37:37]
    fifo_rxq_ram_T_49data <= fifo_rxq_io_enq_bits @[Decoupled.scala 225:17 226:24]
    fifo_rxq_ram_T_49mask <= UInt<1>("h1") @[Decoupled.scala 225:17 226:24]
    fifo_rxq_value <= mux(fifo_rxq_reset, UInt<3>("h0"), fifo_rxq__GEN_5) @[Counter.scala 26:{33,33}]
    fifo_rxq_value_1 <= mux(fifo_rxq_reset, UInt<3>("h0"), fifo_rxq__GEN_6) @[Counter.scala 26:{33,33}]
    fifo_rxq_maybe_full <= mux(fifo_rxq_reset, UInt<1>("h0"), fifo_rxq__GEN_7) @[Decoupled.scala 217:{35,35}]
    node fifo_fire_tx = and(fifo_io_link_tx_ready, fifo_io_link_tx_valid) @[Decoupled.scala 37:37]
    reg fifo_rxen : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), fifo_rxen) @[SPIFIFO.scala 29:17]
    node fifo__GEN_0 = mux(fifo_io_link_rx_valid, UInt<1>("h0"), fifo_rxen) @[SPIFIFO.scala 35:18 36:10 29:17]
    node fifo__T_34 = not(fifo_io_link_fmt_iodir) @[SPIFIFO.scala 39:32]
    node fifo__GEN_1 = mux(fifo_fire_tx, fifo__T_34, fifo__GEN_0) @[SPIFIFO.scala 38:18 39:10]
    node fifo__T_38 = eq(UInt<2>("h0"), fifo_io_link_fmt_proto) @[SPIConsts.scala 13:48]
    node fifo__T_39 = eq(UInt<2>("h1"), fifo_io_link_fmt_proto) @[SPIConsts.scala 13:48]
    node fifo__T_40 = eq(UInt<2>("h2"), fifo_io_link_fmt_proto) @[SPIConsts.scala 13:48]
    node fifo__T_42 = shr(fifo_io_ctrl_fmt_len, 1) @[SPIFIFO.scala 43:73]
    node fifo__T_43 = shr(fifo_io_ctrl_fmt_len, 2) @[SPIFIFO.scala 43:73]
    node fifo__T_46 = mux(fifo__T_38, fifo_io_ctrl_fmt_len, UInt<4>("h0")) @[Mux.scala 19:72]
    node fifo__T_48 = mux(fifo__T_39, fifo__T_42, UInt<3>("h0")) @[Mux.scala 19:72]
    node fifo__T_50 = mux(fifo__T_40, fifo__T_43, UInt<2>("h0")) @[Mux.scala 19:72]
    node fifo__GEN_2 = pad(fifo__T_48, 4) @[Mux.scala 19:72]
    node fifo__T_51 = or(fifo__T_46, fifo__GEN_2) @[Mux.scala 19:72]
    node fifo__GEN_3 = pad(fifo__T_50, 4) @[Mux.scala 19:72]
    node fifo_cnt_quot = or(fifo__T_51, fifo__GEN_3) @[Mux.scala 19:72]
    node fifo__T_55 = bits(fifo_io_ctrl_fmt_len, 0, 0) @[SPIFIFO.scala 44:83]
    node fifo__T_58 = bits(fifo_io_ctrl_fmt_len, 1, 0) @[SPIFIFO.scala 44:83]
    node fifo__T_60 = neq(fifo__T_58, UInt<2>("h0")) @[SPIFIFO.scala 44:92]
    node fifo__T_65 = and(fifo__T_39, fifo__T_55) @[Mux.scala 19:72]
    node fifo__T_67 = and(fifo__T_40, fifo__T_60) @[Mux.scala 19:72]
    node fifo_cnt_rmdr = or(fifo__T_65, fifo__T_67) @[Mux.scala 19:72]
    node fifo__GEN_4 = pad(fifo_cnt_rmdr, 4) @[SPIFIFO.scala 46:27]
    node fifo__T_71 = add(fifo_cnt_quot, fifo__GEN_4) @[SPIFIFO.scala 46:27]
    node fifo__T_72 = tail(fifo__T_71, 1) @[SPIFIFO.scala 46:27]
    reg fifo_cs_mode : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), fifo_cs_mode) @[SPIFIFO.scala 48:24]
    node fifo_cs_mode_hold = eq(fifo_cs_mode, UInt<2>("h2")) @[SPIFIFO.scala 49:31]
    node fifo_cs_mode_off = eq(fifo_cs_mode, UInt<2>("h3")) @[SPIFIFO.scala 50:30]
    node fifo_cs_update = neq(fifo_cs_mode, fifo_io_ctrl_cs_mode) @[SPIFIFO.scala 51:28]
    node fifo__T_77 = or(fifo_cs_mode_hold, fifo_cs_mode_off) @[SPIFIFO.scala 52:33]
    node fifo_cs_clear = not(fifo__T_77) @[SPIFIFO.scala 52:18]
    node fifo__T_81 = and(fifo_fire_tx, fifo_cs_clear) @[SPIFIFO.scala 55:45]
    fifo_io_link_tx_valid <= fifo_txq_io_deq_valid @[SPIFIFO.scala 25:14]
    fifo_io_link_tx_bits <= fifo_txq_io_deq_bits @[SPIFIFO.scala 25:14]
    fifo_io_link_cnt <= pad(fifo__T_72, 8) @[SPIFIFO.scala 46:15]
    fifo_io_link_fmt_proto <= fifo_io_ctrl_fmt_proto @[SPIFIFO.scala 45:15]
    fifo_io_link_fmt_endian <= fifo_io_ctrl_fmt_endian @[SPIFIFO.scala 45:15]
    fifo_io_link_fmt_iodir <= fifo_io_ctrl_fmt_iodir @[SPIFIFO.scala 45:15]
    fifo_io_link_cs_set <= not(fifo_cs_mode_off) @[SPIFIFO.scala 54:21]
    fifo_io_link_cs_clear <= or(fifo_cs_update, fifo__T_81) @[SPIFIFO.scala 55:33]
    fifo_io_tx_ready <= fifo_txq_io_enq_ready @[SPIFIFO.scala 24:14]
    fifo_io_rx_valid <= fifo_rxq_io_deq_valid @[SPIFIFO.scala 33:9]
    fifo_io_rx_bits <= fifo_rxq_io_deq_bits @[SPIFIFO.scala 33:9]
    fifo_io_ip_txwm <= lt(fifo_txq_io_count, fifo_io_ctrl_wm_tx) @[SPIFIFO.scala 60:31]
    fifo_io_ip_rxwm <= gt(fifo_rxq_io_count, fifo_io_ctrl_wm_rx) @[SPIFIFO.scala 61:31]
    fifo_txq_reset <= fifo_reset
    fifo_txq_io_enq_valid <= fifo_io_tx_valid @[SPIFIFO.scala 24:14]
    fifo_txq_io_enq_bits <= fifo_io_tx_bits @[SPIFIFO.scala 24:14]
    fifo_txq_io_deq_ready <= fifo_io_link_tx_ready @[SPIFIFO.scala 25:14]
    fifo_rxq_reset <= fifo_reset
    fifo_rxq_io_enq_valid <= and(fifo_io_link_rx_valid, fifo_rxen) @[SPIFIFO.scala 31:40]
    fifo_rxq_io_enq_bits <= fifo_io_link_rx_bits @[SPIFIFO.scala 32:19]
    fifo_rxq_io_deq_ready <= fifo_io_rx_ready @[SPIFIFO.scala 33:9]
    fifo_rxen <= mux(fifo_reset, UInt<1>("h0"), fifo__GEN_1) @[SPIFIFO.scala 29:{17,17}]
    fifo_cs_mode <= mux(fifo_reset, UInt<2>("h0"), fifo_io_ctrl_cs_mode) @[SPIFIFO.scala 48:{24,24,24}]
    wire mac_reset : UInt<1>
    wire mac_io_port_sck : UInt<1>
    wire mac_io_port_dq_0_i : UInt<1>
    wire mac_io_port_dq_0_o : UInt<1>
    wire mac_io_port_dq_0_oe : UInt<1>
    wire mac_io_port_dq_1_i : UInt<1>
    wire mac_io_port_dq_1_o : UInt<1>
    wire mac_io_port_dq_1_oe : UInt<1>
    wire mac_io_port_dq_2_i : UInt<1>
    wire mac_io_port_dq_2_o : UInt<1>
    wire mac_io_port_dq_2_oe : UInt<1>
    wire mac_io_port_dq_3_i : UInt<1>
    wire mac_io_port_dq_3_o : UInt<1>
    wire mac_io_port_dq_3_oe : UInt<1>
    wire mac_io_port_cs_0 : UInt<1>
    wire mac_io_port_cs_1 : UInt<1>
    wire mac_io_port_cs_2 : UInt<1>
    wire mac_io_port_cs_3 : UInt<1>
    wire mac_io_ctrl_sck_div : UInt<12>
    wire mac_io_ctrl_sck_pol : UInt<1>
    wire mac_io_ctrl_sck_pha : UInt<1>
    wire mac_io_ctrl_dla_cssck : UInt<8>
    wire mac_io_ctrl_dla_sckcs : UInt<8>
    wire mac_io_ctrl_dla_intercs : UInt<8>
    wire mac_io_ctrl_dla_interxfr : UInt<8>
    wire mac_io_ctrl_cs_id : UInt<2>
    wire mac_io_ctrl_cs_dflt_0 : UInt<1>
    wire mac_io_ctrl_cs_dflt_1 : UInt<1>
    wire mac_io_ctrl_cs_dflt_2 : UInt<1>
    wire mac_io_ctrl_cs_dflt_3 : UInt<1>
    wire mac_io_link_tx_ready : UInt<1>
    wire mac_io_link_tx_valid : UInt<1>
    wire mac_io_link_tx_bits : UInt<8>
    wire mac_io_link_rx_valid : UInt<1>
    wire mac_io_link_rx_bits : UInt<8>
    wire mac_io_link_cnt : UInt<8>
    wire mac_io_link_fmt_proto : UInt<2>
    wire mac_io_link_fmt_endian : UInt<1>
    wire mac_io_link_fmt_iodir : UInt<1>
    wire mac_io_link_cs_set : UInt<1>
    wire mac_io_link_cs_clear : UInt<1>
    wire mac_phy_reset : UInt<1>
    wire mac_phy_io_port_sck : UInt<1>
    wire mac_phy_io_port_dq_0_i : UInt<1>
    wire mac_phy_io_port_dq_0_o : UInt<1>
    wire mac_phy_io_port_dq_0_oe : UInt<1>
    wire mac_phy_io_port_dq_1_i : UInt<1>
    wire mac_phy_io_port_dq_1_o : UInt<1>
    wire mac_phy_io_port_dq_1_oe : UInt<1>
    wire mac_phy_io_port_dq_2_i : UInt<1>
    wire mac_phy_io_port_dq_2_o : UInt<1>
    wire mac_phy_io_port_dq_2_oe : UInt<1>
    wire mac_phy_io_port_dq_3_i : UInt<1>
    wire mac_phy_io_port_dq_3_o : UInt<1>
    wire mac_phy_io_port_dq_3_oe : UInt<1>
    wire mac_phy_io_ctrl_sck_div : UInt<12>
    wire mac_phy_io_ctrl_sck_pol : UInt<1>
    wire mac_phy_io_ctrl_sck_pha : UInt<1>
    wire mac_phy_io_ctrl_fmt_proto : UInt<2>
    wire mac_phy_io_ctrl_fmt_endian : UInt<1>
    wire mac_phy_io_ctrl_fmt_iodir : UInt<1>
    wire mac_phy_io_op_ready : UInt<1>
    wire mac_phy_io_op_valid : UInt<1>
    wire mac_phy_io_op_bits_fn : UInt<1>
    wire mac_phy_io_op_bits_stb : UInt<1>
    wire mac_phy_io_op_bits_cnt : UInt<8>
    wire mac_phy_io_op_bits_data : UInt<8>
    wire mac_phy_io_rx_valid : UInt<1>
    wire mac_phy_io_rx_bits : UInt<8>
    reg mac_phy_ctrl_sck_div : UInt<12>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_ctrl_sck_div) @[SPIPhysical.scala 33:17]
    reg mac_phy_ctrl_sck_pol : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_ctrl_sck_pol) @[SPIPhysical.scala 33:17]
    reg mac_phy_ctrl_sck_pha : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_ctrl_sck_pha) @[SPIPhysical.scala 33:17]
    reg mac_phy_ctrl_fmt_proto : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_ctrl_fmt_proto) @[SPIPhysical.scala 33:17]
    reg mac_phy_ctrl_fmt_endian : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_ctrl_fmt_endian) @[SPIPhysical.scala 33:17]
    reg mac_phy_ctrl_fmt_iodir : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 33:17]
    node mac_phy_proto_0 = eq(UInt<2>("h0"), mac_phy_ctrl_fmt_proto) @[SPIConsts.scala 13:48]
    node mac_phy_proto_1 = eq(UInt<2>("h1"), mac_phy_ctrl_fmt_proto) @[SPIConsts.scala 13:48]
    node mac_phy_proto_2 = eq(UInt<2>("h2"), mac_phy_ctrl_fmt_proto) @[SPIConsts.scala 13:48]
    reg mac_phy_setup_d : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_setup_d) @[SPIPhysical.scala 41:20]
    reg mac_phy__T_50 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy__T_50) @[ShiftReg.scala 15:18]
    reg mac_phy__T_51 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy__T_51) @[ShiftReg.scala 15:18]
    reg mac_phy_sample_d : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_sample_d) @[ShiftReg.scala 15:18]
    reg mac_phy__T_53 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy__T_53) @[ShiftReg.scala 15:18]
    reg mac_phy__T_54 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy__T_54) @[ShiftReg.scala 15:18]
    reg mac_phy_last_d : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_last_d) @[ShiftReg.scala 15:18]
    reg mac_phy_scnt : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_scnt) @[SPIPhysical.scala 45:17]
    reg mac_phy_tcnt : UInt<12>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_tcnt) @[SPIPhysical.scala 46:17]
    node mac_phy_stop = eq(mac_phy_scnt, UInt<8>("h0")) @[SPIPhysical.scala 48:20]
    node mac_phy_beat = eq(mac_phy_tcnt, UInt<12>("h0")) @[SPIPhysical.scala 49:20]
    node mac_phy__T_59 = mux(mac_phy_beat, pad(mac_phy_scnt, 12), mac_phy_tcnt) @[SPIPhysical.scala 50:17]
    node mac_phy__T_61 = sub(mac_phy__T_59, UInt<12>("h1")) @[SPIPhysical.scala 50:36]
    node mac_phy_decr = tail(mac_phy__T_61, 1) @[SPIPhysical.scala 50:36]
    node mac_phy_sched = or(mac_phy_stop, mac_phy_beat) @[SPIPhysical.scala 105:15 106:11]
    reg mac_phy_sck : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_sck) @[SPIPhysical.scala 54:16]
    reg mac_phy_cref : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_cref) @[SPIPhysical.scala 55:17]
    node mac_phy_cinv = xor(mac_phy_ctrl_sck_pha, mac_phy_ctrl_sck_pol) @[SPIPhysical.scala 56:27]
    node mac_phy__T_68 = cat(mac_phy_io_port_dq_1_i, mac_phy_io_port_dq_0_i) @[Cat.scala 30:58]
    node mac_phy__T_69 = cat(mac_phy_io_port_dq_3_i, mac_phy_io_port_dq_2_i) @[Cat.scala 30:58]
    node mac_phy_rxd = cat(mac_phy__T_69, mac_phy__T_68) @[Cat.scala 30:58]
    node mac_phy_samples_0 = bits(mac_phy_rxd, 1, 1) @[SPIPhysical.scala 62:24]
    node mac_phy_samples_1 = bits(mac_phy_rxd, 1, 0) @[SPIPhysical.scala 62:32]
    reg mac_phy_buffer : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_buffer) @[SPIPhysical.scala 64:19]
    node mac_phy__T_71 = not(mac_phy_io_ctrl_fmt_endian) @[SPIPhysical.scala 59:20]
    node mac_phy__T_72 = bits(mac_phy_io_op_bits_data, 0, 0) @[SPIPhysical.scala 59:54]
    node mac_phy__T_73 = bits(mac_phy_io_op_bits_data, 1, 1) @[SPIPhysical.scala 59:54]
    node mac_phy__T_74 = bits(mac_phy_io_op_bits_data, 2, 2) @[SPIPhysical.scala 59:54]
    node mac_phy__T_75 = bits(mac_phy_io_op_bits_data, 3, 3) @[SPIPhysical.scala 59:54]
    node mac_phy__T_76 = bits(mac_phy_io_op_bits_data, 4, 4) @[SPIPhysical.scala 59:54]
    node mac_phy__T_77 = bits(mac_phy_io_op_bits_data, 5, 5) @[SPIPhysical.scala 59:54]
    node mac_phy__T_78 = bits(mac_phy_io_op_bits_data, 6, 6) @[SPIPhysical.scala 59:54]
    node mac_phy__T_79 = bits(mac_phy_io_op_bits_data, 7, 7) @[SPIPhysical.scala 59:54]
    node mac_phy__T_80 = cat(mac_phy__T_78, mac_phy__T_79) @[Cat.scala 30:58]
    node mac_phy__T_81 = cat(mac_phy__T_76, mac_phy__T_77) @[Cat.scala 30:58]
    node mac_phy__T_82 = cat(mac_phy__T_81, mac_phy__T_80) @[Cat.scala 30:58]
    node mac_phy__T_83 = cat(mac_phy__T_74, mac_phy__T_75) @[Cat.scala 30:58]
    node mac_phy__T_84 = cat(mac_phy__T_72, mac_phy__T_73) @[Cat.scala 30:58]
    node mac_phy__T_85 = cat(mac_phy__T_84, mac_phy__T_83) @[Cat.scala 30:58]
    node mac_phy__T_86 = cat(mac_phy__T_85, mac_phy__T_82) @[Cat.scala 30:58]
    node mac_phy_buffer_in = mux(mac_phy__T_71, mac_phy_io_op_bits_data, mac_phy__T_86) @[SPIPhysical.scala 59:8]
    node mac_phy__T_87 = and(mac_phy_sample_d, mac_phy_stop) @[SPIPhysical.scala 66:59]
    node mac_phy_shift = or(mac_phy_setup_d, mac_phy__T_87) @[SPIPhysical.scala 66:46]
    node mac_phy__T_88 = bits(mac_phy_buffer, 6, 0) @[SPIPhysical.scala 70:26]
    node mac_phy__T_89 = bits(mac_phy_buffer, 7, 1) @[SPIPhysical.scala 70:42]
    node mac_phy__T_90 = mux(mac_phy_shift, mac_phy__T_88, mac_phy__T_89) @[SPIPhysical.scala 70:12]
    node mac_phy__T_91 = bits(mac_phy_buffer, 0, 0) @[SPIPhysical.scala 71:35]
    node mac_phy__T_92 = mux(mac_phy_sample_d, mac_phy_samples_0, mac_phy__T_91) @[SPIPhysical.scala 71:12]
    node mac_phy__T_93 = cat(mac_phy__T_90, mac_phy__T_92) @[Cat.scala 30:58]
    node mac_phy__T_94 = bits(mac_phy_buffer, 5, 0) @[SPIPhysical.scala 70:26]
    node mac_phy__T_95 = bits(mac_phy_buffer, 7, 2) @[SPIPhysical.scala 70:42]
    node mac_phy__T_96 = mux(mac_phy_shift, mac_phy__T_94, mac_phy__T_95) @[SPIPhysical.scala 70:12]
    node mac_phy__T_97 = bits(mac_phy_buffer, 1, 0) @[SPIPhysical.scala 71:35]
    node mac_phy__T_98 = mux(mac_phy_sample_d, mac_phy_samples_1, mac_phy__T_97) @[SPIPhysical.scala 71:12]
    node mac_phy__T_99 = cat(mac_phy__T_96, mac_phy__T_98) @[Cat.scala 30:58]
    node mac_phy__T_100 = bits(mac_phy_buffer, 3, 0) @[SPIPhysical.scala 70:26]
    node mac_phy__T_101 = bits(mac_phy_buffer, 7, 4) @[SPIPhysical.scala 70:42]
    node mac_phy__T_102 = mux(mac_phy_shift, mac_phy__T_100, mac_phy__T_101) @[SPIPhysical.scala 70:12]
    node mac_phy__T_104 = mux(mac_phy_sample_d, mac_phy_rxd, mac_phy__T_100) @[SPIPhysical.scala 71:12]
    node mac_phy__T_105 = cat(mac_phy__T_102, mac_phy__T_104) @[Cat.scala 30:58]
    node mac_phy__T_108 = mux(mac_phy_proto_0, mac_phy__T_93, UInt<8>("h0")) @[Mux.scala 19:72]
    node mac_phy__T_110 = mux(mac_phy_proto_1, mac_phy__T_99, UInt<8>("h0")) @[Mux.scala 19:72]
    node mac_phy__T_112 = mux(mac_phy_proto_2, mac_phy__T_105, UInt<8>("h0")) @[Mux.scala 19:72]
    node mac_phy__T_113 = or(mac_phy__T_108, mac_phy__T_110) @[Mux.scala 19:72]
    node mac_phy__T_114 = or(mac_phy__T_113, mac_phy__T_112) @[Mux.scala 19:72]
    reg mac_phy_txd : UInt<4>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_txd) @[SPIPhysical.scala 76:16]
    node mac_phy__T_119 = bits(mac_phy_buffer_in, 7, 4) @[SPIPhysical.scala 74:41]
    node mac_phy__T_190 = eq(mac_phy_scnt, UInt<8>("h1")) @[SPIPhysical.scala 122:14]
    node mac_phy__T_194 = not(mac_phy_cref) @[SPIPhysical.scala 124:19]
    node mac_phy__T_195 = and(mac_phy_beat, mac_phy__T_194) @[SPIPhysical.scala 124:16]
    node mac_phy__GEN_17 = or(mac_phy__T_195, mac_phy_stop) @[SPIPhysical.scala 124:26 125:14]
    node mac_phy_accept = mux(mac_phy__T_190, mac_phy__GEN_17, mac_phy_stop) @[SPIPhysical.scala 122:27]
    node mac_phy_txd_in = mux(mac_phy_accept, mac_phy__T_119, mac_phy__T_101) @[SPIPhysical.scala 77:19]
    node mac_phy__T_121 = mux(mac_phy_accept, mac_phy_io_ctrl_fmt_proto, mac_phy_ctrl_fmt_proto) @[SPIPhysical.scala 78:39]
    node mac_phy_txd_sel_0 = eq(UInt<2>("h0"), mac_phy__T_121) @[SPIConsts.scala 13:48]
    node mac_phy_txd_sel_1 = eq(UInt<2>("h1"), mac_phy__T_121) @[SPIConsts.scala 13:48]
    node mac_phy_txd_sel_2 = eq(UInt<2>("h2"), mac_phy__T_121) @[SPIConsts.scala 13:48]
    node mac_phy_txd_shf_0 = bits(mac_phy_txd_in, 3, 3) @[SPIPhysical.scala 79:55]
    node mac_phy_txd_shf_1 = bits(mac_phy_txd_in, 3, 2) @[SPIPhysical.scala 79:55]
    node mac_phy__T_127 = and(mac_phy_txd_sel_0, mac_phy_txd_shf_0) @[Mux.scala 19:72]
    node mac_phy__T_129 = mux(mac_phy_txd_sel_1, mac_phy_txd_shf_1, UInt<2>("h0")) @[Mux.scala 19:72]
    node mac_phy__T_131 = mux(mac_phy_txd_sel_2, mac_phy_txd_in, UInt<4>("h0")) @[Mux.scala 19:72]
    node mac_phy__GEN_68 = pad(mac_phy__T_127, 2) @[Mux.scala 19:72]
    node mac_phy__T_132 = or(mac_phy__GEN_68, mac_phy__T_129) @[Mux.scala 19:72]
    node mac_phy__GEN_69 = pad(mac_phy__T_132, 4) @[Mux.scala 19:72]
    node mac_phy__T_133 = or(mac_phy__GEN_69, mac_phy__T_131) @[Mux.scala 19:72]
    reg mac_phy_done : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_done) @[SPIPhysical.scala 97:17]
    node mac_phy__T_198 = and(mac_phy_accept, mac_phy_done) @[SPIPhysical.scala 131:16]
    node mac_phy__T_202 = not(mac_phy_io_op_bits_fn) @[Conditional.scala 37:30]
    reg mac_phy_xfr : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_phy_xfr) @[SPIPhysical.scala 103:16]
    node mac_phy__GEN_3 = and(mac_phy_xfr, mac_phy__T_194) @[SPIPhysical.scala 111:18 114:15]
    node mac_phy__GEN_8 = and(mac_phy_beat, mac_phy__GEN_3) @[SPIPhysical.scala 109:17]
    node mac_phy__GEN_15 = mux(mac_phy_stop, UInt<1>("h0"), mac_phy__GEN_8) @[SPIPhysical.scala 105:15]
    node mac_phy__GEN_18 = mux(mac_phy__T_195, UInt<1>("h0"), mac_phy__GEN_15) @[SPIPhysical.scala 124:26 126:13]
    node mac_phy__GEN_22 = mux(mac_phy__T_190, mac_phy__GEN_18, mac_phy__GEN_15) @[SPIPhysical.scala 122:27]
    node mac_phy__GEN_37 = or(mac_phy__T_202, mac_phy__GEN_22) @[Conditional.scala 40:58 SPIPhysical.scala 144:17]
    node mac_phy__GEN_50 = mux(mac_phy_io_op_valid, mac_phy__GEN_37, mac_phy__GEN_22) @[SPIPhysical.scala 133:24]
    node mac_phy_setup = mux(mac_phy__T_198, mac_phy__GEN_50, mac_phy__GEN_22) @[SPIPhysical.scala 131:25]
    node mac_phy__GEN_0 = mux(mac_phy_setup, mac_phy__T_133, mac_phy_txd) @[SPIPhysical.scala 76:16 80:16 81:9]
    node mac_phy__T_137 = and(mac_phy_proto_1, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 85:49]
    node mac_phy_txen_2 = and(mac_phy_proto_2, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 85:49]
    node mac_phy_txen_1 = or(mac_phy__T_137, mac_phy_txen_2) @[SPIPhysical.scala 85:82]
    node mac_phy__T_160 = or(mac_phy_done, mac_phy_last_d) @[SPIPhysical.scala 98:16]
    node mac_phy__T_162 = not(mac_phy_ctrl_fmt_endian) @[SPIPhysical.scala 59:20]
    node mac_phy__T_164 = bits(mac_phy_buffer, 1, 1) @[SPIPhysical.scala 59:54]
    node mac_phy__T_165 = bits(mac_phy_buffer, 2, 2) @[SPIPhysical.scala 59:54]
    node mac_phy__T_166 = bits(mac_phy_buffer, 3, 3) @[SPIPhysical.scala 59:54]
    node mac_phy__T_167 = bits(mac_phy_buffer, 4, 4) @[SPIPhysical.scala 59:54]
    node mac_phy__T_168 = bits(mac_phy_buffer, 5, 5) @[SPIPhysical.scala 59:54]
    node mac_phy__T_169 = bits(mac_phy_buffer, 6, 6) @[SPIPhysical.scala 59:54]
    node mac_phy__T_170 = bits(mac_phy_buffer, 7, 7) @[SPIPhysical.scala 59:54]
    node mac_phy__T_171 = cat(mac_phy__T_169, mac_phy__T_170) @[Cat.scala 30:58]
    node mac_phy__T_172 = cat(mac_phy__T_167, mac_phy__T_168) @[Cat.scala 30:58]
    node mac_phy__T_173 = cat(mac_phy__T_172, mac_phy__T_171) @[Cat.scala 30:58]
    node mac_phy__T_174 = cat(mac_phy__T_165, mac_phy__T_166) @[Cat.scala 30:58]
    node mac_phy__T_175 = cat(mac_phy__T_91, mac_phy__T_164) @[Cat.scala 30:58]
    node mac_phy__T_176 = cat(mac_phy__T_175, mac_phy__T_174) @[Cat.scala 30:58]
    node mac_phy__T_177 = cat(mac_phy__T_176, mac_phy__T_173) @[Cat.scala 30:58]
    node mac_phy__T_184 = xor(mac_phy_cref, mac_phy_cinv) @[SPIPhysical.scala 112:21]
    node mac_phy__GEN_1 = mux(mac_phy_xfr, mac_phy__T_184, mac_phy_sck) @[SPIPhysical.scala 111:18 112:13 54:16]
    node mac_phy__GEN_2 = and(mac_phy_xfr, mac_phy_cref) @[SPIPhysical.scala 111:18 113:16]
    node mac_phy__GEN_4 = mux(mac_phy__T_194, mac_phy_decr, pad(mac_phy_scnt, 12)) @[SPIPhysical.scala 116:20 117:14 45:17]
    node mac_phy__GEN_5 = mux(mac_phy_beat, mac_phy__T_194, mac_phy_cref) @[SPIPhysical.scala 109:17 110:12 55:17]
    node mac_phy__GEN_6 = mux(mac_phy_beat, mac_phy__GEN_1, mac_phy_sck) @[SPIPhysical.scala 109:17 54:16]
    node mac_phy__GEN_7 = and(mac_phy_beat, mac_phy__GEN_2) @[SPIPhysical.scala 109:17]
    node mac_phy__GEN_9 = mux(mac_phy_beat, mac_phy__GEN_4, pad(mac_phy_scnt, 12)) @[SPIPhysical.scala 109:17 45:17]
    node mac_phy__GEN_12 = mux(mac_phy_stop, mac_phy_cref, mac_phy__GEN_5) @[SPIPhysical.scala 105:15 55:17]
    node mac_phy__GEN_13 = mux(mac_phy_stop, mac_phy_sck, mac_phy__GEN_6) @[SPIPhysical.scala 105:15 54:16]
    node mac_phy_sample = mux(mac_phy_stop, UInt<1>("h0"), mac_phy__GEN_7) @[SPIPhysical.scala 105:15]
    node mac_phy__GEN_16 = mux(mac_phy_stop, pad(mac_phy_scnt, 12), mac_phy__GEN_9) @[SPIPhysical.scala 105:15 45:17]
    node mac_phy__T_191 = and(mac_phy_beat, mac_phy_cref) @[SPIPhysical.scala 123:18]
    node mac_phy__T_192 = and(mac_phy__T_191, mac_phy_xfr) @[SPIPhysical.scala 123:26]
    node mac_phy__GEN_19 = mux(mac_phy__T_195, mac_phy_ctrl_sck_pol, mac_phy__GEN_13) @[SPIPhysical.scala 124:26 127:11]
    node mac_phy_last = and(mac_phy__T_190, mac_phy__T_192) @[SPIPhysical.scala 122:27 123:10]
    node mac_phy__GEN_23 = mux(mac_phy__T_190, mac_phy__GEN_19, mac_phy__GEN_13) @[SPIPhysical.scala 122:27]
    node mac_phy__GEN_24 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_fmt_proto, mac_phy_ctrl_fmt_proto) @[SPIPhysical.scala 135:21 136:18 33:17]
    node mac_phy__GEN_25 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_fmt_endian, mac_phy_ctrl_fmt_endian) @[SPIPhysical.scala 135:21 136:18 33:17]
    node mac_phy__GEN_26 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_fmt_iodir, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 135:21 136:18 33:17]
    node mac_phy__T_205 = eq(mac_phy_io_op_bits_cnt, UInt<8>("h0")) @[SPIPhysical.scala 145:27]
    node mac_phy__GEN_27 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_sck_pol, mac_phy__GEN_23) @[SPIPhysical.scala 149:25 150:17]
    node mac_phy__GEN_28 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_sck_div, mac_phy_ctrl_sck_div) @[SPIPhysical.scala 149:25 151:22 33:17]
    node mac_phy__GEN_29 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_sck_pol, mac_phy_ctrl_sck_pol) @[SPIPhysical.scala 149:25 151:22 33:17]
    node mac_phy__GEN_30 = mux(mac_phy_io_op_bits_stb, mac_phy_io_ctrl_sck_pha, mac_phy_ctrl_sck_pha) @[SPIPhysical.scala 149:25 151:22 33:17]
    node mac_phy__GEN_31 = mux(mac_phy_io_op_bits_fn, mac_phy__GEN_27, mac_phy__GEN_23) @[Conditional.scala 39:67]
    node mac_phy__GEN_32 = mux(mac_phy_io_op_bits_fn, mac_phy__GEN_28, mac_phy_ctrl_sck_div) @[Conditional.scala 39:67 SPIPhysical.scala 33:17]
    node mac_phy__GEN_33 = mux(mac_phy_io_op_bits_fn, mac_phy__GEN_29, mac_phy_ctrl_sck_pol) @[Conditional.scala 39:67 SPIPhysical.scala 33:17]
    node mac_phy__GEN_34 = mux(mac_phy_io_op_bits_fn, mac_phy__GEN_30, mac_phy_ctrl_sck_pha) @[Conditional.scala 39:67 SPIPhysical.scala 33:17]
    node mac_phy__GEN_35 = mux(mac_phy__T_202, mac_phy_buffer_in, mac_phy__T_114) @[Conditional.scala 40:58 SPIPhysical.scala 142:18 67:10]
    node mac_phy__GEN_36 = mux(mac_phy__T_202, mac_phy_cinv, mac_phy__GEN_31) @[Conditional.scala 40:58 SPIPhysical.scala 143:15]
    node mac_phy__GEN_38 = mux(mac_phy__T_202, mac_phy__T_205, mac_phy__T_160) @[Conditional.scala 40:58 SPIPhysical.scala 145:16 98:8]
    node mac_phy__GEN_40 = mux(mac_phy__T_202, mac_phy_ctrl_sck_div, mac_phy__GEN_32) @[Conditional.scala 40:58 SPIPhysical.scala 33:17]
    node mac_phy__GEN_41 = mux(mac_phy__T_202, mac_phy_ctrl_sck_pol, mac_phy__GEN_33) @[Conditional.scala 40:58 SPIPhysical.scala 33:17]
    node mac_phy__GEN_42 = mux(mac_phy__T_202, mac_phy_ctrl_sck_pha, mac_phy__GEN_34) @[Conditional.scala 40:58 SPIPhysical.scala 33:17]
    node mac_phy__GEN_43 = mux(mac_phy_io_op_valid, pad(mac_phy_io_op_bits_cnt, 12), mac_phy__GEN_16) @[SPIPhysical.scala 133:24 134:12]
    node mac_phy__GEN_44 = mux(mac_phy_io_op_valid, mac_phy__GEN_24, mac_phy_ctrl_fmt_proto) @[SPIPhysical.scala 133:24 33:17]
    node mac_phy__GEN_45 = mux(mac_phy_io_op_valid, mac_phy__GEN_25, mac_phy_ctrl_fmt_endian) @[SPIPhysical.scala 133:24 33:17]
    node mac_phy__GEN_46 = mux(mac_phy_io_op_valid, mac_phy__GEN_26, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 133:24 33:17]
    node mac_phy__GEN_47 = mux(mac_phy_io_op_valid, mac_phy__T_202, mac_phy_xfr) @[SPIPhysical.scala 103:16 133:24]
    node mac_phy__GEN_48 = mux(mac_phy_io_op_valid, mac_phy__GEN_35, mac_phy__T_114) @[SPIPhysical.scala 133:24 67:10]
    node mac_phy__GEN_49 = mux(mac_phy_io_op_valid, mac_phy__GEN_36, mac_phy__GEN_23) @[SPIPhysical.scala 133:24]
    node mac_phy__GEN_51 = mux(mac_phy_io_op_valid, mac_phy__GEN_38, mac_phy__T_160) @[SPIPhysical.scala 133:24 98:8]
    node mac_phy__GEN_52 = mux(mac_phy_io_op_valid, mac_phy__GEN_40, mac_phy_ctrl_sck_div) @[SPIPhysical.scala 133:24 33:17]
    node mac_phy__GEN_53 = mux(mac_phy_io_op_valid, mac_phy__GEN_41, mac_phy_ctrl_sck_pol) @[SPIPhysical.scala 133:24 33:17]
    node mac_phy__GEN_54 = mux(mac_phy_io_op_valid, mac_phy__GEN_42, mac_phy_ctrl_sck_pha) @[SPIPhysical.scala 133:24 33:17]
    node mac_phy__GEN_56 = mux(mac_phy__T_198, mac_phy__GEN_43, mac_phy__GEN_16) @[SPIPhysical.scala 131:25]
    node mac_phy__GEN_64 = mux(mac_phy__T_198, mac_phy__GEN_51, mac_phy__T_160) @[SPIPhysical.scala 131:25 98:8]
    node mac_phy__GEN_70 = mux(mac_phy_reset, UInt<12>("h0"), mac_phy__GEN_56) @[SPIPhysical.scala 45:{17,17}]
    mac_phy_io_port_sck <= mac_phy_sck @[SPIPhysical.scala 88:15]
    mac_phy_io_port_dq_0_o <= bits(mac_phy_txd, 0, 0) @[SPIPhysical.scala 90:24]
    mac_phy_io_port_dq_0_oe <= or(mac_phy_proto_0, mac_phy_txen_1) @[SPIPhysical.scala 85:82]
    mac_phy_io_port_dq_1_o <= bits(mac_phy_txd, 1, 1) @[SPIPhysical.scala 90:24]
    mac_phy_io_port_dq_1_oe <= or(mac_phy__T_137, mac_phy_txen_2) @[SPIPhysical.scala 85:82]
    mac_phy_io_port_dq_2_o <= bits(mac_phy_txd, 2, 2) @[SPIPhysical.scala 90:24]
    mac_phy_io_port_dq_2_oe <= and(mac_phy_proto_2, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 85:49]
    mac_phy_io_port_dq_3_o <= bits(mac_phy_txd, 3, 3) @[SPIPhysical.scala 90:24]
    mac_phy_io_port_dq_3_oe <= and(mac_phy_proto_2, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 85:49]
    mac_phy_io_op_ready <= and(mac_phy_accept, mac_phy_done) @[SPIPhysical.scala 131:16]
    mac_phy_io_rx_valid <= mac_phy_done @[SPIPhysical.scala 100:15]
    mac_phy_io_rx_bits <= mux(mac_phy__T_162, mac_phy_buffer, mac_phy__T_177) @[SPIPhysical.scala 59:8]
    mac_phy_ctrl_sck_div <= mux(mac_phy__T_198, mac_phy__GEN_52, mac_phy_ctrl_sck_div) @[SPIPhysical.scala 131:25 33:17]
    mac_phy_ctrl_sck_pol <= mux(mac_phy__T_198, mac_phy__GEN_53, mac_phy_ctrl_sck_pol) @[SPIPhysical.scala 131:25 33:17]
    mac_phy_ctrl_sck_pha <= mux(mac_phy__T_198, mac_phy__GEN_54, mac_phy_ctrl_sck_pha) @[SPIPhysical.scala 131:25 33:17]
    mac_phy_ctrl_fmt_proto <= mux(mac_phy__T_198, mac_phy__GEN_44, mac_phy_ctrl_fmt_proto) @[SPIPhysical.scala 131:25 33:17]
    mac_phy_ctrl_fmt_endian <= mux(mac_phy__T_198, mac_phy__GEN_45, mac_phy_ctrl_fmt_endian) @[SPIPhysical.scala 131:25 33:17]
    mac_phy_ctrl_fmt_iodir <= mux(mac_phy__T_198, mac_phy__GEN_46, mac_phy_ctrl_fmt_iodir) @[SPIPhysical.scala 131:25 33:17]
    mac_phy_setup_d <= mux(mac_phy__T_198, mac_phy__GEN_50, mac_phy__GEN_22) @[SPIPhysical.scala 131:25]
    mac_phy__T_50 <= mux(mac_phy_reset, UInt<1>("h0"), mac_phy_sample) @[ShiftReg.scala 15:{18,18,18}]
    mac_phy__T_51 <= mux(mac_phy_reset, UInt<1>("h0"), mac_phy__T_50) @[ShiftReg.scala 15:{18,18,18}]
    mac_phy_sample_d <= mux(mac_phy_reset, UInt<1>("h0"), mac_phy__T_51) @[ShiftReg.scala 15:{18,18,18}]
    mac_phy__T_53 <= mux(mac_phy_reset, UInt<1>("h0"), mac_phy_last) @[ShiftReg.scala 15:{18,18,18}]
    mac_phy__T_54 <= mux(mac_phy_reset, UInt<1>("h0"), mac_phy__T_53) @[ShiftReg.scala 15:{18,18,18}]
    mac_phy_last_d <= mux(mac_phy_reset, UInt<1>("h0"), mac_phy__T_54) @[ShiftReg.scala 15:{18,18,18}]
    mac_phy_scnt <= bits(mac_phy__GEN_70, 7, 0) @[SPIPhysical.scala 45:{17,17}]
    mac_phy_tcnt <= mux(mac_phy_sched, mac_phy_ctrl_sck_div, mac_phy_decr) @[SPIPhysical.scala 52:14]
    mac_phy_sck <= mux(mac_phy__T_198, mac_phy__GEN_49, mac_phy__GEN_23) @[SPIPhysical.scala 131:25]
    mac_phy_cref <= or(mac_phy_reset, mac_phy__GEN_12) @[SPIPhysical.scala 55:{17,17}]
    mac_phy_buffer <= mux(mac_phy__T_198, mac_phy__GEN_48, mac_phy__T_114) @[SPIPhysical.scala 131:25 67:10]
    mac_phy_txd <= mux(mac_phy_reset, UInt<4>("h0"), mac_phy__GEN_0) @[SPIPhysical.scala 76:{16,16}]
    mac_phy_done <= or(mac_phy_reset, mac_phy__GEN_64) @[SPIPhysical.scala 97:{17,17}]
    mac_phy_xfr <= mux(mac_phy__T_198, mac_phy__GEN_47, mac_phy_xfr) @[SPIPhysical.scala 103:16 131:25]
    reg mac_cs_id : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_id) @[SPIMedia.scala 42:15]
    reg mac_cs_dflt_0 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_dflt_0) @[SPIMedia.scala 42:15]
    reg mac_cs_dflt_1 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_dflt_1) @[SPIMedia.scala 42:15]
    reg mac_cs_dflt_2 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_dflt_2) @[SPIMedia.scala 42:15]
    reg mac_cs_dflt_3 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_dflt_3) @[SPIMedia.scala 42:15]
    reg mac_cs_set : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_set) @[SPIMedia.scala 43:19]
    node mac__T_68 = dshl(mac_io_link_cs_set, mac_io_ctrl_cs_id) @[SPIBundle.scala 47:19]
    node mac__T_69 = cat(mac_io_ctrl_cs_dflt_1, mac_io_ctrl_cs_dflt_0) @[Cat.scala 30:58]
    node mac__T_70 = cat(mac_io_ctrl_cs_dflt_3, mac_io_ctrl_cs_dflt_2) @[Cat.scala 30:58]
    node mac__T_71 = cat(mac__T_70, mac__T_69) @[Cat.scala 30:58]
    node mac__T_72 = xor(mac__T_71, mac__T_68) @[SPIBundle.scala 48:33]
    node mac_cs_active_0 = bits(mac__T_72, 0, 0) @[SPIBundle.scala 49:32]
    node mac_cs_active_1 = bits(mac__T_72, 1, 1) @[SPIBundle.scala 49:32]
    node mac_cs_active_2 = bits(mac__T_72, 2, 2) @[SPIBundle.scala 49:32]
    node mac_cs_active_3 = bits(mac__T_72, 3, 3) @[SPIBundle.scala 49:32]
    node mac__T_85 = cat(mac_cs_active_1, mac_cs_active_0) @[SPIMedia.scala 45:30]
    node mac__T_86 = cat(mac_cs_active_3, mac_cs_active_2) @[SPIMedia.scala 45:30]
    node mac__T_87 = cat(mac__T_86, mac__T_85) @[SPIMedia.scala 45:30]
    node mac__T_88 = cat(mac_cs_dflt_1, mac_cs_dflt_0) @[SPIMedia.scala 45:49]
    node mac__T_89 = cat(mac_cs_dflt_3, mac_cs_dflt_2) @[SPIMedia.scala 45:49]
    node mac__T_90 = cat(mac__T_89, mac__T_88) @[SPIMedia.scala 45:49]
    node mac_cs_update = neq(mac__T_87, mac__T_90) @[SPIMedia.scala 45:37]
    reg mac_clear : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_clear) @[SPIMedia.scala 47:18]
    reg mac_cs_assert : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), mac_cs_assert) @[SPIMedia.scala 48:22]
    node mac_cs_deassert = or(mac_clear, mac_cs_update) @[SPIMedia.scala 49:27]
    node mac__T_98 = and(mac_io_link_cs_clear, mac_cs_assert) @[SPIMedia.scala 51:39]
    node mac__T_99 = or(mac_clear, mac__T_98) @[SPIMedia.scala 51:18]
    node mac_continuous = eq(mac_io_ctrl_dla_interxfr, UInt<8>("h0")) @[SPIMedia.scala 53:42]
    reg mac_state : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), mac_state) @[SPIMedia.scala 64:18]
    node mac__T_104 = eq(UInt<2>("h0"), mac_state) @[Conditional.scala 37:30]
    node mac__GEN_0 = mux(mac_phy_io_op_ready, UInt<2>("h2"), mac_state) @[SPIMedia.scala 64:18 71:27 72:19]
    node mac__T_107 = and(mac_phy_io_op_ready, mac_phy_io_op_valid) @[Decoupled.scala 37:37]
    node mac__GEN_1 = mux(mac__T_107, UInt<2>("h1"), mac_state) @[SPIMedia.scala 64:18 80:28 81:19]
    node mac__GEN_2 = mux(mac_cs_deassert, mac_io_ctrl_dla_sckcs, mac_io_link_cnt) @[SPIMedia.scala 39:15 69:28 70:23]
    node mac__GEN_3 = mux(mac_cs_deassert, mac__GEN_0, mac__GEN_1) @[SPIMedia.scala 69:28]
    node mac__GEN_5 = mux(mac_cs_deassert, UInt<1>("h0"), UInt<1>("h1")) @[SPIMedia.scala 38:15 69:28 76:23]
    node mac__GEN_6 = or(mac_cs_deassert, mac_io_link_tx_valid) @[SPIMedia.scala 36:12 69:28 78:20]
    node mac__GEN_7 = mux(mac_cs_deassert, UInt<1>("h0"), mac_phy_io_op_ready) @[SPIMedia.scala 60:20 69:28 79:28]
    node mac__GEN_8 = or(mac_phy_io_op_ready, mac_cs_assert) @[SPIMedia.scala 87:25 88:21 48:22]
    node mac__GEN_9 = mux(mac_phy_io_op_ready, mac_io_link_cs_set, mac_cs_set) @[SPIMedia.scala 87:25 89:18 43:19]
    node mac__GEN_10 = mux(mac_phy_io_op_ready, mac_cs_active_0, mac_cs_dflt_0) @[SPIMedia.scala 42:15 87:25 90:19]
    node mac__GEN_11 = mux(mac_phy_io_op_ready, mac_cs_active_1, mac_cs_dflt_1) @[SPIMedia.scala 42:15 87:25 90:19]
    node mac__GEN_12 = mux(mac_phy_io_op_ready, mac_cs_active_2, mac_cs_dflt_2) @[SPIMedia.scala 42:15 87:25 90:19]
    node mac__GEN_13 = mux(mac_phy_io_op_ready, mac_cs_active_3, mac_cs_dflt_3) @[SPIMedia.scala 42:15 87:25 90:19]
    node mac__GEN_14 = mux(mac_io_link_tx_valid, mac_io_ctrl_dla_cssck, UInt<8>("h0")) @[SPIMedia.scala 84:38 86:21 94:21]
    node mac__GEN_15 = mux(mac_io_link_tx_valid, mac__GEN_8, mac_cs_assert) @[SPIMedia.scala 48:22 84:38]
    node mac__GEN_16 = mux(mac_io_link_tx_valid, mac__GEN_9, mac_cs_set) @[SPIMedia.scala 43:19 84:38]
    node mac__GEN_17 = mux(mac_io_link_tx_valid, mac__GEN_10, mac_io_ctrl_cs_dflt_0) @[SPIMedia.scala 84:38 96:12]
    node mac__GEN_18 = mux(mac_io_link_tx_valid, mac__GEN_11, mac_io_ctrl_cs_dflt_1) @[SPIMedia.scala 84:38 96:12]
    node mac__GEN_19 = mux(mac_io_link_tx_valid, mac__GEN_12, mac_io_ctrl_cs_dflt_2) @[SPIMedia.scala 84:38 96:12]
    node mac__GEN_20 = mux(mac_io_link_tx_valid, mac__GEN_13, mac_io_ctrl_cs_dflt_3) @[SPIMedia.scala 84:38 96:12]
    node mac__GEN_21 = mux(mac_io_link_tx_valid, UInt<1>("h0"), UInt<1>("h1")) @[SPIMedia.scala 38:15 84:38 95:21]
    node mac__GEN_22 = mux(mac_io_link_tx_valid, mac_cs_id, mac_io_ctrl_cs_id) @[SPIMedia.scala 42:15 84:38 96:12]
    node mac__GEN_23 = mux(mac_cs_assert, mac__GEN_2, mac__GEN_14) @[SPIMedia.scala 68:24]
    node mac__GEN_24 = mux(mac_cs_assert, mac__GEN_3, mac_state) @[SPIMedia.scala 64:18 68:24]
    node mac__GEN_25 = mux(mac_cs_assert, mac_cs_deassert, UInt<1>("h1")) @[SPIMedia.scala 37:14 68:24]
    node mac__GEN_26 = mux(mac_cs_assert, mac__GEN_5, mac__GEN_21) @[SPIMedia.scala 68:24]
    node mac__GEN_27 = mux(mac_cs_assert, mac__GEN_6, UInt<1>("h1")) @[SPIMedia.scala 36:12 68:24]
    node mac__GEN_28 = and(mac_cs_assert, mac__GEN_7) @[SPIMedia.scala 60:20 68:24]
    node mac__GEN_29 = mux(mac_cs_assert, mac_cs_assert, mac__GEN_15) @[SPIMedia.scala 48:22 68:24]
    node mac__GEN_30 = mux(mac_cs_assert, mac_cs_set, mac__GEN_16) @[SPIMedia.scala 43:19 68:24]
    node mac__GEN_31 = mux(mac_cs_assert, mac_cs_dflt_0, mac__GEN_17) @[SPIMedia.scala 42:15 68:24]
    node mac__GEN_32 = mux(mac_cs_assert, mac_cs_dflt_1, mac__GEN_18) @[SPIMedia.scala 42:15 68:24]
    node mac__GEN_33 = mux(mac_cs_assert, mac_cs_dflt_2, mac__GEN_19) @[SPIMedia.scala 42:15 68:24]
    node mac__GEN_34 = mux(mac_cs_assert, mac_cs_dflt_3, mac__GEN_20) @[SPIMedia.scala 42:15 68:24]
    node mac__GEN_35 = mux(mac_cs_assert, mac_cs_id, mac__GEN_22) @[SPIMedia.scala 42:15 68:24]
    node mac__T_111 = eq(UInt<2>("h1"), mac_state) @[Conditional.scala 37:30]
    node mac__T_113 = not(mac_continuous) @[SPIMedia.scala 102:19]
    node mac__T_114 = or(mac_phy_io_op_ready, mac_continuous) @[SPIMedia.scala 104:22]
    node mac__GEN_36 = mux(mac__T_114, UInt<2>("h0"), mac_state) @[SPIMedia.scala 104:37 105:15 64:18]
    node mac__T_115 = eq(UInt<2>("h2"), mac_state) @[Conditional.scala 37:30]
    node mac__T_119 = dshl(mac_cs_set, mac_cs_id) @[SPIBundle.scala 47:19]
    node mac__T_123 = xor(mac__T_90, mac__T_119) @[SPIBundle.scala 48:33]
    node mac__T_124 = bits(mac__T_123, 0, 0) @[SPIBundle.scala 49:32]
    node mac__T_125 = bits(mac__T_123, 1, 1) @[SPIBundle.scala 49:32]
    node mac__T_126 = bits(mac__T_123, 2, 2) @[SPIBundle.scala 49:32]
    node mac__T_127 = bits(mac__T_123, 3, 3) @[SPIBundle.scala 49:32]
    node mac__GEN_37 = mux(mac_phy_io_op_ready, mac__T_124, mac_cs_dflt_0) @[SPIMedia.scala 115:23 116:17 42:15]
    node mac__GEN_38 = mux(mac_phy_io_op_ready, mac__T_125, mac_cs_dflt_1) @[SPIMedia.scala 115:23 116:17 42:15]
    node mac__GEN_39 = mux(mac_phy_io_op_ready, mac__T_126, mac_cs_dflt_2) @[SPIMedia.scala 115:23 116:17 42:15]
    node mac__GEN_40 = mux(mac_phy_io_op_ready, mac__T_127, mac_cs_dflt_3) @[SPIMedia.scala 115:23 116:17 42:15]
    node mac__GEN_41 = mux(mac_phy_io_op_ready, UInt<2>("h0"), mac_state) @[SPIMedia.scala 115:23 117:15 64:18]
    node mac__GEN_42 = mux(mac__T_115, mac_io_ctrl_dla_intercs, mac_io_link_cnt) @[Conditional.scala 39:67 SPIMedia.scala 111:19 39:15]
    node mac__GEN_44 = mux(mac__T_115, UInt<1>("h0"), mac_cs_assert) @[Conditional.scala 39:67 SPIMedia.scala 113:17 48:22]
    node mac__GEN_45 = mux(mac__T_115, UInt<1>("h0"), mac__T_99) @[Conditional.scala 39:67 SPIMedia.scala 114:13 51:9]
    node mac__GEN_46 = mux(mac__T_115, mac__GEN_37, mac_cs_dflt_0) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_47 = mux(mac__T_115, mac__GEN_38, mac_cs_dflt_1) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_48 = mux(mac__T_115, mac__GEN_39, mac_cs_dflt_2) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_49 = mux(mac__T_115, mac__GEN_40, mac_cs_dflt_3) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_50 = mux(mac__T_115, mac__GEN_41, mac_state) @[Conditional.scala 39:67 SPIMedia.scala 64:18]
    node mac__GEN_51 = mux(mac__T_111, mac__T_113, UInt<1>("h1")) @[Conditional.scala 39:67 SPIMedia.scala 102:16 36:12]
    node mac__GEN_52 = mux(mac__T_111, mac_io_ctrl_dla_interxfr, mac__GEN_42) @[Conditional.scala 39:67 SPIMedia.scala 103:19]
    node mac__GEN_53 = mux(mac__T_111, mac__GEN_36, mac__GEN_50) @[Conditional.scala 39:67]
    node mac__GEN_54 = mux(mac__T_111, UInt<1>("h0"), mac__T_115) @[Conditional.scala 39:67 SPIMedia.scala 38:15]
    node mac__GEN_55 = mux(mac__T_111, mac_cs_assert, mac__GEN_44) @[Conditional.scala 39:67 SPIMedia.scala 48:22]
    node mac__GEN_56 = mux(mac__T_111, mac__T_99, mac__GEN_45) @[Conditional.scala 39:67 SPIMedia.scala 51:9]
    node mac__GEN_57 = mux(mac__T_111, mac_cs_dflt_0, mac__GEN_46) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_58 = mux(mac__T_111, mac_cs_dflt_1, mac__GEN_47) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_59 = mux(mac__T_111, mac_cs_dflt_2, mac__GEN_48) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_60 = mux(mac__T_111, mac_cs_dflt_3, mac__GEN_49) @[Conditional.scala 39:67 SPIMedia.scala 42:15]
    node mac__GEN_62 = mux(mac__T_104, mac__GEN_24, mac__GEN_53) @[Conditional.scala 40:58]
    node mac__GEN_67 = mux(mac__T_104, mac__GEN_29, mac__GEN_55) @[Conditional.scala 40:58]
    node mac__GEN_74 = mux(mac__T_104, mac__T_99, mac__GEN_56) @[Conditional.scala 40:58 SPIMedia.scala 51:9]
    mac_io_port_sck <= mac_phy_io_port_sck @[SPIMedia.scala 55:15]
    mac_io_port_dq_0_o <= mac_phy_io_port_dq_0_o @[SPIMedia.scala 56:14]
    mac_io_port_dq_0_oe <= mac_phy_io_port_dq_0_oe @[SPIMedia.scala 56:14]
    mac_io_port_dq_1_o <= mac_phy_io_port_dq_1_o @[SPIMedia.scala 56:14]
    mac_io_port_dq_1_oe <= mac_phy_io_port_dq_1_oe @[SPIMedia.scala 56:14]
    mac_io_port_dq_2_o <= mac_phy_io_port_dq_2_o @[SPIMedia.scala 56:14]
    mac_io_port_dq_2_oe <= mac_phy_io_port_dq_2_oe @[SPIMedia.scala 56:14]
    mac_io_port_dq_3_o <= mac_phy_io_port_dq_3_o @[SPIMedia.scala 56:14]
    mac_io_port_dq_3_oe <= mac_phy_io_port_dq_3_oe @[SPIMedia.scala 56:14]
    mac_io_port_cs_0 <= mac_cs_dflt_0 @[SPIMedia.scala 57:14]
    mac_io_port_cs_1 <= mac_cs_dflt_1 @[SPIMedia.scala 57:14]
    mac_io_port_cs_2 <= mac_cs_dflt_2 @[SPIMedia.scala 57:14]
    mac_io_port_cs_3 <= mac_cs_dflt_3 @[SPIMedia.scala 57:14]
    mac_io_link_tx_ready <= and(mac__T_104, mac__GEN_28) @[Conditional.scala 40:58 SPIMedia.scala 60:20]
    mac_io_link_rx_valid <= mac_phy_io_rx_valid @[SPIMedia.scala 59:14]
    mac_io_link_rx_bits <= mac_phy_io_rx_bits @[SPIMedia.scala 59:14]
    mac_phy_reset <= mac_reset
    mac_phy_io_port_dq_0_i <= mac_io_port_dq_0_i @[SPIMedia.scala 56:14]
    mac_phy_io_port_dq_1_i <= mac_io_port_dq_1_i @[SPIMedia.scala 56:14]
    mac_phy_io_port_dq_2_i <= mac_io_port_dq_2_i @[SPIMedia.scala 56:14]
    mac_phy_io_port_dq_3_i <= mac_io_port_dq_3_i @[SPIMedia.scala 56:14]
    mac_phy_io_ctrl_sck_div <= mac_io_ctrl_sck_div @[SPIMedia.scala 32:19]
    mac_phy_io_ctrl_sck_pol <= mac_io_ctrl_sck_pol @[SPIMedia.scala 32:19]
    mac_phy_io_ctrl_sck_pha <= mac_io_ctrl_sck_pha @[SPIMedia.scala 32:19]
    mac_phy_io_ctrl_fmt_proto <= mac_io_link_fmt_proto @[SPIMedia.scala 33:19]
    mac_phy_io_ctrl_fmt_endian <= mac_io_link_fmt_endian @[SPIMedia.scala 33:19]
    mac_phy_io_ctrl_fmt_iodir <= mac_io_link_fmt_iodir @[SPIMedia.scala 33:19]
    mac_phy_io_op_valid <= mux(mac__T_104, mac__GEN_27, mac__GEN_51) @[Conditional.scala 40:58]
    mac_phy_io_op_bits_fn <= mux(mac__T_104, mac__GEN_25, UInt<1>("h1")) @[Conditional.scala 40:58 SPIMedia.scala 37:14]
    mac_phy_io_op_bits_stb <= mux(mac__T_104, mac__GEN_26, mac__GEN_54) @[Conditional.scala 40:58]
    mac_phy_io_op_bits_cnt <= mux(mac__T_104, mac__GEN_23, mac__GEN_52) @[Conditional.scala 40:58]
    mac_phy_io_op_bits_data <= mac_io_link_tx_bits @[SPIMedia.scala 40:16]
    mac_cs_id <= mux(mac__T_104, mac__GEN_35, mac_cs_id) @[Conditional.scala 40:58 SPIMedia.scala 42:15]
    mac_cs_dflt_0 <= mux(mac__T_104, mac__GEN_31, mac__GEN_57) @[Conditional.scala 40:58]
    mac_cs_dflt_1 <= mux(mac__T_104, mac__GEN_32, mac__GEN_58) @[Conditional.scala 40:58]
    mac_cs_dflt_2 <= mux(mac__T_104, mac__GEN_33, mac__GEN_59) @[Conditional.scala 40:58]
    mac_cs_dflt_3 <= mux(mac__T_104, mac__GEN_34, mac__GEN_60) @[Conditional.scala 40:58]
    mac_cs_set <= mux(mac__T_104, mac__GEN_30, mac_cs_set) @[Conditional.scala 40:58 SPIMedia.scala 43:19]
    mac_clear <= mux(mac_reset, UInt<1>("h0"), mac__GEN_74) @[SPIMedia.scala 47:{18,18}]
    mac_cs_assert <= mux(mac_reset, UInt<1>("h0"), mac__GEN_67) @[SPIMedia.scala 48:{22,22}]
    mac_state <= mux(mac_reset, UInt<2>("h0"), mac__GEN_62) @[SPIMedia.scala 64:{18,18}]
    reg ctrl_fmt_proto : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_fmt_proto) @[TLSPI.scala 58:17]
    reg ctrl_fmt_endian : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_fmt_endian) @[TLSPI.scala 58:17]
    reg ctrl_fmt_iodir : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_fmt_iodir) @[TLSPI.scala 58:17]
    reg ctrl_fmt_len : UInt<4>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_fmt_len) @[TLSPI.scala 58:17]
    reg ctrl_sck_div : UInt<12>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_sck_div) @[TLSPI.scala 58:17]
    reg ctrl_sck_pol : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_sck_pol) @[TLSPI.scala 58:17]
    reg ctrl_sck_pha : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_sck_pha) @[TLSPI.scala 58:17]
    reg ctrl_cs_id : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_cs_id) @[TLSPI.scala 58:17]
    reg ctrl_cs_dflt_0 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_cs_dflt_0) @[TLSPI.scala 58:17]
    reg ctrl_cs_dflt_1 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_cs_dflt_1) @[TLSPI.scala 58:17]
    reg ctrl_cs_dflt_2 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_cs_dflt_2) @[TLSPI.scala 58:17]
    reg ctrl_cs_dflt_3 : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_cs_dflt_3) @[TLSPI.scala 58:17]
    reg ctrl_cs_mode : UInt<2>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_cs_mode) @[TLSPI.scala 58:17]
    reg ctrl_dla_cssck : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_dla_cssck) @[TLSPI.scala 58:17]
    reg ctrl_dla_sckcs : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_dla_sckcs) @[TLSPI.scala 58:17]
    reg ctrl_dla_intercs : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_dla_intercs) @[TLSPI.scala 58:17]
    reg ctrl_dla_interxfr : UInt<8>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_dla_interxfr) @[TLSPI.scala 58:17]
    reg ctrl_wm_tx : UInt<4>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_wm_tx) @[TLSPI.scala 58:17]
    reg ctrl_wm_rx : UInt<4>, in_clock with :
      reset => (UInt<1>("h0"), ctrl_wm_rx) @[TLSPI.scala 58:17]
    reg ie_txwm : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ie_txwm) @[TLSPI.scala 71:15]
    reg ie_rxwm : UInt<1>, in_clock with :
      reset => (UInt<1>("h0"), ie_rxwm) @[TLSPI.scala 71:15]
    node _T_261 = and(fifo_io_ip_txwm, ie_txwm) @[TLSPI.scala 74:25]
    node _T_262 = and(fifo_io_ip_rxwm, ie_rxwm) @[TLSPI.scala 74:49]
    node _T_269 = not(fifo_io_tx_ready) @[RegMapFIFO.scala 24:9]
    node _T_272 = not(fifo_io_rx_valid) @[RegMapFIFO.scala 45:21]
    node _T_281 = eq(auto_r_in_a_bits_opcode, UInt<3>("h4")) @[RegisterRouter.scala 55:36]
    node _T_282 = shr(auto_r_in_a_bits_address, 2) @[Edges.scala 183:34]
    node _T_283 = cat(auto_r_in_a_bits_source, auto_r_in_a_bits_size) @[Cat.scala 30:58]
    node _T_277_bits_index = bits(_T_282, 9, 0) @[RegisterRouter.scala 54:18 56:19]
    node _T_366 = and(_T_277_bits_index, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_368 = eq(_T_366, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_374 = xor(_T_277_bits_index, UInt<10>("h5")) @[RegisterRouter.scala 62:24]
    node _T_375 = and(_T_374, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_377 = eq(_T_375, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_383 = xor(_T_277_bits_index, UInt<10>("ha")) @[RegisterRouter.scala 62:24]
    node _T_384 = and(_T_383, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_386 = eq(_T_384, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_392 = xor(_T_277_bits_index, UInt<10>("h14")) @[RegisterRouter.scala 62:24]
    node _T_393 = and(_T_392, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_395 = eq(_T_393, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_401 = xor(_T_277_bits_index, UInt<10>("h1d")) @[RegisterRouter.scala 62:24]
    node _T_402 = and(_T_401, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_404 = eq(_T_402, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_410 = xor(_T_277_bits_index, UInt<10>("h1")) @[RegisterRouter.scala 62:24]
    node _T_411 = and(_T_410, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_413 = eq(_T_411, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_419 = xor(_T_277_bits_index, UInt<10>("h6")) @[RegisterRouter.scala 62:24]
    node _T_420 = and(_T_419, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_422 = eq(_T_420, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_428 = xor(_T_277_bits_index, UInt<10>("h1c")) @[RegisterRouter.scala 62:24]
    node _T_429 = and(_T_428, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_431 = eq(_T_429, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_437 = xor(_T_277_bits_index, UInt<10>("h15")) @[RegisterRouter.scala 62:24]
    node _T_438 = and(_T_437, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_440 = eq(_T_438, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_446 = xor(_T_277_bits_index, UInt<10>("h12")) @[RegisterRouter.scala 62:24]
    node _T_447 = and(_T_446, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_449 = eq(_T_447, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_455 = xor(_T_277_bits_index, UInt<10>("h10")) @[RegisterRouter.scala 62:24]
    node _T_456 = and(_T_455, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_458 = eq(_T_456, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_464 = xor(_T_277_bits_index, UInt<10>("hb")) @[RegisterRouter.scala 62:24]
    node _T_465 = and(_T_464, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_467 = eq(_T_465, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_473 = xor(_T_277_bits_index, UInt<10>("h13")) @[RegisterRouter.scala 62:24]
    node _T_474 = and(_T_473, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_476 = eq(_T_474, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_482 = xor(_T_277_bits_index, UInt<10>("h4")) @[RegisterRouter.scala 62:24]
    node _T_483 = and(_T_482, UInt<10>("h3e0")) @[RegisterRouter.scala 62:24]
    node _T_485 = eq(_T_483, UInt<10>("h0")) @[RegisterRouter.scala 62:24]
    node _T_662 = bits(auto_r_in_a_bits_mask, 0, 0) @[Bitwise.scala 27:51]
    node _T_663 = bits(auto_r_in_a_bits_mask, 1, 1) @[Bitwise.scala 27:51]
    node _T_664 = bits(auto_r_in_a_bits_mask, 2, 2) @[Bitwise.scala 27:51]
    node _T_665 = bits(auto_r_in_a_bits_mask, 3, 3) @[Bitwise.scala 27:51]
    node _T_669 = mux(_T_662, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_673 = mux(_T_663, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_677 = mux(_T_664, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_681 = mux(_T_665, UInt<8>("hff"), UInt<8>("h0")) @[Bitwise.scala 72:12]
    node _T_682 = cat(_T_673, _T_669) @[Cat.scala 30:58]
    node _T_683 = cat(_T_681, _T_677) @[Cat.scala 30:58]
    node _T_684 = cat(_T_683, _T_682) @[Cat.scala 30:58]
    node _T_708 = bits(_T_684, 11, 0) @[RegisterRouter.scala 62:24]
    node _T_712 = not(_T_708) @[RegisterRouter.scala 62:24]
    node _T_714 = eq(_T_712, UInt<12>("h0")) @[RegisterRouter.scala 62:24]
    node _T_2007 = bits(_T_277_bits_index, 4, 4) @[RegisterRouter.scala 62:24]
    node _T_2006 = bits(_T_277_bits_index, 3, 3) @[RegisterRouter.scala 62:24]
    node _T_2014 = cat(_T_2007, _T_2006) @[Cat.scala 30:58]
    node _T_2005 = bits(_T_277_bits_index, 2, 2) @[RegisterRouter.scala 62:24]
    node _T_2015 = cat(_T_2014, _T_2005) @[Cat.scala 30:58]
    node _T_2004 = bits(_T_277_bits_index, 1, 1) @[RegisterRouter.scala 62:24]
    node _T_2003 = bits(_T_277_bits_index, 0, 0) @[RegisterRouter.scala 62:24]
    node _T_2013 = cat(_T_2004, _T_2003) @[Cat.scala 30:58]
    node _T_2016 = cat(_T_2015, _T_2013) @[Cat.scala 30:58]
    node _T_2085 = and(auto_r_in_a_valid, auto_r_in_d_ready) @[RegisterRouter.scala 62:24]
    node _T_2086 = and(_T_2085, _T_281) @[RegisterRouter.scala 62:24]
    node _T_2018 = dshl(UInt<1>("h1"), _T_2016) @[OneHot.scala 45:35]
    node _T_2019 = bits(_T_2018, 0, 0) @[RegisterRouter.scala 62:24]
    node _T_2382 = not(_T_281) @[RegisterRouter.scala 62:24]
    node _T_2383 = and(_T_2085, _T_2382) @[RegisterRouter.scala 62:24]
    node _T_2386 = and(_T_2383, _T_2019) @[RegisterRouter.scala 62:24]
    node _T_2387 = and(_T_2386, _T_368) @[RegisterRouter.scala 62:24]
    node _T_724 = and(_T_2387, _T_714) @[RegisterRouter.scala 62:24]
    node _T_728 = bits(auto_r_in_a_bits_data, 11, 0) @[RegisterRouter.scala 62:24]
    node _GEN_0 = mux(_T_724, _T_728, ctrl_sck_div) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_752 = bits(_T_684, 0, 0) @[RegisterRouter.scala 62:24]
    node _T_756 = not(_T_752) @[RegisterRouter.scala 62:24]
    node _T_758 = not(_T_756) @[RegisterRouter.scala 62:24]
    node _T_2024 = bits(_T_2018, 5, 5) @[RegisterRouter.scala 62:24]
    node _T_2426 = and(_T_2383, _T_2024) @[RegisterRouter.scala 62:24]
    node _T_2427 = and(_T_2426, _T_377) @[RegisterRouter.scala 62:24]
    node _T_768 = and(_T_2427, _T_758) @[RegisterRouter.scala 62:24]
    node _T_772 = bits(auto_r_in_a_bits_data, 0, 0) @[RegisterRouter.scala 62:24]
    node _GEN_1 = mux(_T_768, _T_772, ctrl_cs_dflt_0) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_796 = bits(_T_684, 1, 1) @[RegisterRouter.scala 62:24]
    node _T_800 = not(_T_796) @[RegisterRouter.scala 62:24]
    node _T_802 = not(_T_800) @[RegisterRouter.scala 62:24]
    node _T_812 = and(_T_2427, _T_802) @[RegisterRouter.scala 62:24]
    node _T_816 = bits(auto_r_in_a_bits_data, 1, 1) @[RegisterRouter.scala 62:24]
    node _GEN_2 = mux(_T_812, _T_816, ctrl_cs_dflt_1) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_835 = shl(ctrl_cs_dflt_1, 1) @[RegisterRouter.scala 62:24]
    node _GEN_213 = pad(ctrl_cs_dflt_0, 2) @[RegisterRouter.scala 62:24]
    node _T_839 = or(_GEN_213, _T_835) @[RegisterRouter.scala 62:24]
    node _T_840 = bits(_T_684, 2, 2) @[RegisterRouter.scala 62:24]
    node _T_844 = not(_T_840) @[RegisterRouter.scala 62:24]
    node _T_846 = not(_T_844) @[RegisterRouter.scala 62:24]
    node _T_856 = and(_T_2427, _T_846) @[RegisterRouter.scala 62:24]
    node _T_860 = bits(auto_r_in_a_bits_data, 2, 2) @[RegisterRouter.scala 62:24]
    node _GEN_3 = mux(_T_856, _T_860, ctrl_cs_dflt_2) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_879 = shl(ctrl_cs_dflt_2, 2) @[RegisterRouter.scala 62:24]
    node _GEN_214 = pad(_T_839, 3) @[RegisterRouter.scala 62:24]
    node _T_883 = or(_GEN_214, _T_879) @[RegisterRouter.scala 62:24]
    node _T_884 = bits(_T_684, 3, 3) @[RegisterRouter.scala 62:24]
    node _T_888 = not(_T_884) @[RegisterRouter.scala 62:24]
    node _T_890 = not(_T_888) @[RegisterRouter.scala 62:24]
    node _T_900 = and(_T_2427, _T_890) @[RegisterRouter.scala 62:24]
    node _T_904 = bits(auto_r_in_a_bits_data, 3, 3) @[RegisterRouter.scala 62:24]
    node _GEN_4 = mux(_T_900, _T_904, ctrl_cs_dflt_3) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_923 = shl(ctrl_cs_dflt_3, 3) @[RegisterRouter.scala 62:24]
    node _GEN_215 = pad(_T_883, 4) @[RegisterRouter.scala 62:24]
    node _T_927 = or(_GEN_215, _T_923) @[RegisterRouter.scala 62:24]
    node _T_928 = bits(_T_684, 7, 0) @[RegisterRouter.scala 62:24]
    node _T_930 = neq(_T_928, UInt<8>("h0")) @[RegisterRouter.scala 62:24]
    node _T_932 = not(_T_928) @[RegisterRouter.scala 62:24]
    node _T_934 = eq(_T_932, UInt<8>("h0")) @[RegisterRouter.scala 62:24]
    node _T_2029 = bits(_T_2018, 10, 10) @[RegisterRouter.scala 62:24]
    node _T_2466 = and(_T_2383, _T_2029) @[RegisterRouter.scala 62:24]
    node _T_2467 = and(_T_2466, _T_386) @[RegisterRouter.scala 62:24]
    node _T_944 = and(_T_2467, _T_934) @[RegisterRouter.scala 62:24]
    node _T_948 = bits(auto_r_in_a_bits_data, 7, 0) @[RegisterRouter.scala 62:24]
    node _GEN_5 = mux(_T_944, _T_948, ctrl_dla_cssck) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_972 = bits(_T_684, 23, 16) @[RegisterRouter.scala 62:24]
    node _T_976 = not(_T_972) @[RegisterRouter.scala 62:24]
    node _T_978 = eq(_T_976, UInt<8>("h0")) @[RegisterRouter.scala 62:24]
    node _T_988 = and(_T_2467, _T_978) @[RegisterRouter.scala 62:24]
    node _T_992 = bits(auto_r_in_a_bits_data, 23, 16) @[RegisterRouter.scala 62:24]
    node _GEN_6 = mux(_T_988, _T_992, ctrl_dla_sckcs) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1011 = shl(ctrl_dla_sckcs, 16) @[RegisterRouter.scala 62:24]
    node _GEN_216 = pad(ctrl_dla_cssck, 24) @[RegisterRouter.scala 62:24]
    node _T_1015 = or(_GEN_216, _T_1011) @[RegisterRouter.scala 62:24]
    node _T_1016 = bits(_T_684, 3, 0) @[RegisterRouter.scala 62:24]
    node _T_1020 = not(_T_1016) @[RegisterRouter.scala 62:24]
    node _T_1022 = eq(_T_1020, UInt<4>("h0")) @[RegisterRouter.scala 62:24]
    node _T_2039 = bits(_T_2018, 20, 20) @[RegisterRouter.scala 62:24]
    node _T_2546 = and(_T_2383, _T_2039) @[RegisterRouter.scala 62:24]
    node _T_2547 = and(_T_2546, _T_395) @[RegisterRouter.scala 62:24]
    node _T_1032 = and(_T_2547, _T_1022) @[RegisterRouter.scala 62:24]
    node _T_1036 = bits(auto_r_in_a_bits_data, 3, 0) @[RegisterRouter.scala 62:24]
    node _GEN_7 = mux(_T_1032, _T_1036, ctrl_wm_tx) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1099 = fifo_io_ip_txwm @[RegisterRouter.scala 62:24]
    node _T_1143 = shl(fifo_io_ip_rxwm, 1) @[RegisterRouter.scala 62:24]
    node _GEN_217 = pad(_T_1099, 2) @[RegisterRouter.scala 62:24]
    node _T_1147 = or(_GEN_217, _T_1143) @[RegisterRouter.scala 62:24]
    node _T_2020 = bits(_T_2018, 1, 1) @[RegisterRouter.scala 62:24]
    node _T_2394 = and(_T_2383, _T_2020) @[RegisterRouter.scala 62:24]
    node _T_2395 = and(_T_2394, _T_413) @[RegisterRouter.scala 62:24]
    node _T_1164 = and(_T_2395, _T_758) @[RegisterRouter.scala 62:24]
    node _GEN_8 = mux(_T_1164, _T_772, ctrl_sck_pha) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1208 = and(_T_2395, _T_802) @[RegisterRouter.scala 62:24]
    node _GEN_9 = mux(_T_1208, _T_816, ctrl_sck_pol) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1231 = shl(ctrl_sck_pol, 1) @[RegisterRouter.scala 62:24]
    node _GEN_218 = pad(ctrl_sck_pha, 2) @[RegisterRouter.scala 62:24]
    node _T_1235 = or(_GEN_218, _T_1231) @[RegisterRouter.scala 62:24]
    node _T_1236 = bits(_T_684, 1, 0) @[RegisterRouter.scala 62:24]
    node _T_1240 = not(_T_1236) @[RegisterRouter.scala 62:24]
    node _T_1242 = eq(_T_1240, UInt<2>("h0")) @[RegisterRouter.scala 62:24]
    node _T_2025 = bits(_T_2018, 6, 6) @[RegisterRouter.scala 62:24]
    node _T_2434 = and(_T_2383, _T_2025) @[RegisterRouter.scala 62:24]
    node _T_2435 = and(_T_2434, _T_422) @[RegisterRouter.scala 62:24]
    node _T_1252 = and(_T_2435, _T_1242) @[RegisterRouter.scala 62:24]
    node _T_1256 = bits(auto_r_in_a_bits_data, 1, 0) @[RegisterRouter.scala 62:24]
    node _GEN_10 = mux(_T_1252, _T_1256, ctrl_cs_mode) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_2047 = bits(_T_2018, 28, 28) @[RegisterRouter.scala 62:24]
    node _T_2610 = and(_T_2383, _T_2047) @[RegisterRouter.scala 62:24]
    node _T_2611 = and(_T_2610, _T_431) @[RegisterRouter.scala 62:24]
    node _T_1296 = and(_T_2611, _T_758) @[RegisterRouter.scala 62:24]
    node _GEN_11 = mux(_T_1296, _T_772, ie_txwm) @[RegField.scala 135:{88,92} TLSPI.scala 71:15]
    node _T_1340 = and(_T_2611, _T_802) @[RegisterRouter.scala 62:24]
    node _GEN_12 = mux(_T_1340, _T_816, ie_rxwm) @[RegField.scala 135:{88,92} TLSPI.scala 71:15]
    node _T_1363 = shl(ie_rxwm, 1) @[RegisterRouter.scala 62:24]
    node _GEN_219 = pad(ie_txwm, 2) @[RegisterRouter.scala 62:24]
    node _T_1367 = or(_GEN_219, _T_1363) @[RegisterRouter.scala 62:24]
    node _T_2040 = bits(_T_2018, 21, 21) @[RegisterRouter.scala 62:24]
    node _T_2554 = and(_T_2383, _T_2040) @[RegisterRouter.scala 62:24]
    node _T_2555 = and(_T_2554, _T_440) @[RegisterRouter.scala 62:24]
    node _T_1384 = and(_T_2555, _T_1022) @[RegisterRouter.scala 62:24]
    node _GEN_13 = mux(_T_1384, _T_1036, ctrl_wm_rx) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_2037 = bits(_T_2018, 18, 18) @[RegisterRouter.scala 62:24]
    node _T_2530 = and(_T_2383, _T_2037) @[RegisterRouter.scala 62:24]
    node _T_2531 = and(_T_2530, _T_449) @[RegisterRouter.scala 62:24]
    node _T_1428 = and(_T_2531, _T_934) @[RegisterRouter.scala 62:24]
    node _T_1513 = bits(_T_684, 31, 31) @[RegisterRouter.scala 62:24]
    node _T_1514 = not(_T_1513) @[RegisterRouter.scala 62:24]
    node _T_1516 = not(_T_1514) @[RegisterRouter.scala 62:24]
    node _T_1520 = and(_T_2531, _T_1516) @[RegisterRouter.scala 62:24]
    node _T_1523 = bits(auto_r_in_a_bits_data, 31, 31) @[RegisterRouter.scala 62:24]
    node _T_1526 = and(_T_1520, _T_1523) @[RegMapFIFO.scala 26:26]
    node _T_1435 = not(_T_1526) @[RegMapFIFO.scala 18:33]
    node _T_1544 = shl(_T_269, 31) @[RegisterRouter.scala 62:24]
    node _T_2035 = bits(_T_2018, 16, 16) @[RegisterRouter.scala 62:24]
    node _T_2514 = and(_T_2383, _T_2035) @[RegisterRouter.scala 62:24]
    node _T_2515 = and(_T_2514, _T_458) @[RegisterRouter.scala 62:24]
    node _T_1565 = and(_T_2515, _T_1242) @[RegisterRouter.scala 62:24]
    node _GEN_14 = mux(_T_1565, _T_1256, ctrl_fmt_proto) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1609 = and(_T_2515, _T_846) @[RegisterRouter.scala 62:24]
    node _GEN_15 = mux(_T_1609, _T_860, ctrl_fmt_endian) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1632 = shl(ctrl_fmt_endian, 2) @[RegisterRouter.scala 62:24]
    node _GEN_220 = pad(ctrl_fmt_proto, 3) @[RegisterRouter.scala 62:24]
    node _T_1636 = or(_GEN_220, _T_1632) @[RegisterRouter.scala 62:24]
    node _T_1653 = and(_T_2515, _T_890) @[RegisterRouter.scala 62:24]
    node _GEN_16 = mux(_T_1653, _T_904, ctrl_fmt_iodir) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1676 = shl(ctrl_fmt_iodir, 3) @[RegisterRouter.scala 62:24]
    node _GEN_221 = pad(_T_1636, 4) @[RegisterRouter.scala 62:24]
    node _T_1680 = or(_GEN_221, _T_1676) @[RegisterRouter.scala 62:24]
    node _T_1681 = bits(_T_684, 19, 16) @[RegisterRouter.scala 62:24]
    node _T_1685 = not(_T_1681) @[RegisterRouter.scala 62:24]
    node _T_1687 = eq(_T_1685, UInt<4>("h0")) @[RegisterRouter.scala 62:24]
    node _T_1697 = and(_T_2515, _T_1687) @[RegisterRouter.scala 62:24]
    node _T_1701 = bits(auto_r_in_a_bits_data, 19, 16) @[RegisterRouter.scala 62:24]
    node _GEN_17 = mux(_T_1697, _T_1701, ctrl_fmt_len) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1720 = shl(ctrl_fmt_len, 16) @[RegisterRouter.scala 62:24]
    node _GEN_222 = pad(_T_1680, 20) @[RegisterRouter.scala 62:24]
    node _T_1724 = or(_GEN_222, _T_1720) @[RegisterRouter.scala 62:24]
    node _T_2030 = bits(_T_2018, 11, 11) @[RegisterRouter.scala 62:24]
    node _T_2474 = and(_T_2383, _T_2030) @[RegisterRouter.scala 62:24]
    node _T_2475 = and(_T_2474, _T_467) @[RegisterRouter.scala 62:24]
    node _T_1741 = and(_T_2475, _T_934) @[RegisterRouter.scala 62:24]
    node _GEN_18 = mux(_T_1741, _T_948, ctrl_dla_intercs) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1785 = and(_T_2475, _T_978) @[RegisterRouter.scala 62:24]
    node _GEN_19 = mux(_T_1785, _T_992, ctrl_dla_interxfr) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _T_1808 = shl(ctrl_dla_interxfr, 16) @[RegisterRouter.scala 62:24]
    node _GEN_223 = pad(ctrl_dla_intercs, 24) @[RegisterRouter.scala 62:24]
    node _T_1812 = or(_GEN_223, _T_1808) @[RegisterRouter.scala 62:24]
    node _T_2038 = bits(_T_2018, 19, 19) @[RegisterRouter.scala 62:24]
    node _T_2241 = and(_T_2086, _T_2038) @[RegisterRouter.scala 62:24]
    node _T_2242 = and(_T_2241, _T_476) @[RegisterRouter.scala 62:24]
    node _T_1852 = fifo_io_rx_bits @[RegisterRouter.scala 62:24]
    node _T_1900 = pad(_T_1852, 31) @[RegisterRouter.scala 62:24]
    node _T_1940 = shl(_T_272, 31) @[RegisterRouter.scala 62:24]
    node _GEN_224 = pad(_T_1900, 32) @[RegisterRouter.scala 62:24]
    node _T_1944 = or(_GEN_224, _T_1940) @[RegisterRouter.scala 62:24]
    node _T_2023 = bits(_T_2018, 4, 4) @[RegisterRouter.scala 62:24]
    node _T_2418 = and(_T_2383, _T_2023) @[RegisterRouter.scala 62:24]
    node _T_2419 = and(_T_2418, _T_485) @[RegisterRouter.scala 62:24]
    node _T_1961 = and(_T_2419, _T_1242) @[RegisterRouter.scala 62:24]
    node _GEN_20 = mux(_T_1961, _T_1256, ctrl_cs_id) @[RegField.scala 135:{88,92} TLSPI.scala 58:17]
    node _GEN_150 = mux(eq(UInt<5>("h1"), _T_2016), _T_413, _T_368) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_225 = eq(UInt<5>("h2"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_151 = or(_GEN_225, _GEN_150) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_226 = eq(UInt<5>("h3"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_152 = or(_GEN_226, _GEN_151) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_153 = mux(eq(UInt<5>("h4"), _T_2016), _T_485, _GEN_152) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_154 = mux(eq(UInt<5>("h5"), _T_2016), _T_377, _GEN_153) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_155 = mux(eq(UInt<5>("h6"), _T_2016), _T_422, _GEN_154) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_227 = eq(UInt<5>("h7"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_156 = or(_GEN_227, _GEN_155) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_228 = eq(UInt<5>("h8"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_157 = or(_GEN_228, _GEN_156) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_229 = eq(UInt<5>("h9"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_158 = or(_GEN_229, _GEN_157) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_159 = mux(eq(UInt<5>("ha"), _T_2016), _T_386, _GEN_158) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_160 = mux(eq(UInt<5>("hb"), _T_2016), _T_467, _GEN_159) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_230 = eq(UInt<5>("hc"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_161 = or(_GEN_230, _GEN_160) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_231 = eq(UInt<5>("hd"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_162 = or(_GEN_231, _GEN_161) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_232 = eq(UInt<5>("he"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_163 = or(_GEN_232, _GEN_162) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_233 = eq(UInt<5>("hf"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_164 = or(_GEN_233, _GEN_163) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_165 = mux(eq(UInt<5>("h10"), _T_2016), _T_458, _GEN_164) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_234 = eq(UInt<5>("h11"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_166 = or(_GEN_234, _GEN_165) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_167 = mux(eq(UInt<5>("h12"), _T_2016), _T_449, _GEN_166) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_168 = mux(eq(UInt<5>("h13"), _T_2016), _T_476, _GEN_167) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_169 = mux(eq(UInt<5>("h14"), _T_2016), _T_395, _GEN_168) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_170 = mux(eq(UInt<5>("h15"), _T_2016), _T_440, _GEN_169) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_235 = eq(UInt<5>("h16"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_171 = or(_GEN_235, _GEN_170) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_236 = eq(UInt<5>("h17"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_172 = or(_GEN_236, _GEN_171) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_237 = eq(UInt<5>("h18"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_173 = or(_GEN_237, _GEN_172) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_238 = eq(UInt<5>("h19"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_174 = or(_GEN_238, _GEN_173) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_239 = eq(UInt<5>("h1a"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_175 = or(_GEN_239, _GEN_174) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_240 = eq(UInt<5>("h1b"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_176 = or(_GEN_240, _GEN_175) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_177 = mux(eq(UInt<5>("h1c"), _T_2016), _T_431, _GEN_176) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_178 = mux(eq(UInt<5>("h1d"), _T_2016), _T_404, _GEN_177) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_241 = eq(UInt<5>("h1e"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_179 = or(_GEN_241, _GEN_178) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_242 = eq(UInt<5>("h1f"), _T_2016) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_180 = or(_GEN_242, _GEN_179) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_0 = pad(ctrl_sck_div, 32) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_1 = pad(_T_1235, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_182 = mux(eq(UInt<5>("h1"), _T_2016), _T_3319_1, _T_3319_0) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_183 = mux(eq(UInt<5>("h2"), _T_2016), UInt<32>("h0"), _GEN_182) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_184 = mux(eq(UInt<5>("h3"), _T_2016), UInt<32>("h0"), _GEN_183) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_4 = pad(ctrl_cs_id, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_185 = mux(eq(UInt<5>("h4"), _T_2016), _T_3319_4, _GEN_184) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_5 = pad(_T_927, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_186 = mux(eq(UInt<5>("h5"), _T_2016), _T_3319_5, _GEN_185) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_6 = pad(ctrl_cs_mode, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_187 = mux(eq(UInt<5>("h6"), _T_2016), _T_3319_6, _GEN_186) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_188 = mux(eq(UInt<5>("h7"), _T_2016), UInt<32>("h0"), _GEN_187) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_189 = mux(eq(UInt<5>("h8"), _T_2016), UInt<32>("h0"), _GEN_188) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_190 = mux(eq(UInt<5>("h9"), _T_2016), UInt<32>("h0"), _GEN_189) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_10 = pad(_T_1015, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_191 = mux(eq(UInt<5>("ha"), _T_2016), _T_3319_10, _GEN_190) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_11 = pad(_T_1812, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_192 = mux(eq(UInt<5>("hb"), _T_2016), _T_3319_11, _GEN_191) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_193 = mux(eq(UInt<5>("hc"), _T_2016), UInt<32>("h0"), _GEN_192) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_194 = mux(eq(UInt<5>("hd"), _T_2016), UInt<32>("h0"), _GEN_193) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_195 = mux(eq(UInt<5>("he"), _T_2016), UInt<32>("h0"), _GEN_194) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_196 = mux(eq(UInt<5>("hf"), _T_2016), UInt<32>("h0"), _GEN_195) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_16 = pad(_T_1724, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_197 = mux(eq(UInt<5>("h10"), _T_2016), _T_3319_16, _GEN_196) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_198 = mux(eq(UInt<5>("h11"), _T_2016), UInt<32>("h0"), _GEN_197) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_199 = mux(eq(UInt<5>("h12"), _T_2016), _T_1544, _GEN_198) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_200 = mux(eq(UInt<5>("h13"), _T_2016), _T_1944, _GEN_199) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_20 = pad(ctrl_wm_tx, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_201 = mux(eq(UInt<5>("h14"), _T_2016), _T_3319_20, _GEN_200) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_21 = pad(ctrl_wm_rx, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_202 = mux(eq(UInt<5>("h15"), _T_2016), _T_3319_21, _GEN_201) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_203 = mux(eq(UInt<5>("h16"), _T_2016), UInt<32>("h0"), _GEN_202) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_204 = mux(eq(UInt<5>("h17"), _T_2016), UInt<32>("h0"), _GEN_203) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_205 = mux(eq(UInt<5>("h18"), _T_2016), UInt<32>("h0"), _GEN_204) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_206 = mux(eq(UInt<5>("h19"), _T_2016), UInt<32>("h0"), _GEN_205) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_207 = mux(eq(UInt<5>("h1a"), _T_2016), UInt<32>("h0"), _GEN_206) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_208 = mux(eq(UInt<5>("h1b"), _T_2016), UInt<32>("h0"), _GEN_207) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_28 = pad(_T_1367, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_209 = mux(eq(UInt<5>("h1c"), _T_2016), _T_3319_28, _GEN_208) @[RegisterRouter.scala 62:{24,24}]
    node _T_3319_29 = pad(_T_1147, 32) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_210 = mux(eq(UInt<5>("h1d"), _T_2016), _T_3319_29, _GEN_209) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_211 = mux(eq(UInt<5>("h1e"), _T_2016), UInt<32>("h0"), _GEN_210) @[RegisterRouter.scala 62:{24,24}]
    node _GEN_212 = mux(eq(UInt<5>("h1f"), _T_2016), UInt<32>("h0"), _GEN_211) @[RegisterRouter.scala 62:{24,24}]
    auto_int_out_0 <= or(_T_261, _T_262) @[TLSPI.scala 74:37]
    auto_r_in_a_ready <= auto_r_in_d_ready @[RegisterRouter.scala 62:24]
    auto_r_in_b_valid <= UInt<1>("h0") @[Nodes.scala 329:76 RegisterRouter.scala 80:22]
    auto_r_in_b_bits_opcode <= UInt<3>("h0") @[LazyModule.scala 171:31]
    auto_r_in_b_bits_param <= UInt<2>("h0") @[LazyModule.scala 171:31]
    auto_r_in_b_bits_size <= UInt<2>("h0") @[LazyModule.scala 171:31]
    auto_r_in_b_bits_source <= UInt<7>("h0") @[LazyModule.scala 171:31]
    auto_r_in_b_bits_address <= UInt<29>("h0") @[LazyModule.scala 171:31]
    auto_r_in_b_bits_mask <= UInt<4>("h0") @[LazyModule.scala 171:31]
    auto_r_in_b_bits_data <= UInt<32>("h0") @[LazyModule.scala 171:31]
    auto_r_in_c_ready <= UInt<1>("h1") @[Nodes.scala 329:76 RegisterRouter.scala 81:22]
    auto_r_in_d_valid <= auto_r_in_a_valid @[RegisterRouter.scala 62:24]
    auto_r_in_d_bits_opcode <= pad(_T_281, 3) @[Nodes.scala 329:76 RegisterRouter.scala 77:19]
    auto_r_in_d_bits_param <= UInt<2>("h0") @[Edges.scala 646:17 648:15]
    auto_r_in_d_bits_size <= bits(_T_283, 1, 0) @[RegisterRouter.scala 73:35]
    auto_r_in_d_bits_source <= bits(_T_283, 8, 2) @[RegisterRouter.scala 72:35]
    auto_r_in_d_bits_sink <= UInt<1>("h0") @[Edges.scala 646:17 651:15]
    auto_r_in_d_bits_data <= mux(_GEN_180, _GEN_212, UInt<32>("h0")) @[RegisterRouter.scala 62:24]
    auto_r_in_d_bits_error <= UInt<1>("h0") @[Edges.scala 646:17 653:15]
    auto_r_in_e_ready <= UInt<1>("h1") @[Nodes.scala 329:76 RegisterRouter.scala 82:22]
    io_port_sck <= mac_io_port_sck @[TLSPI.scala 62:11]
    io_port_dq_0_o <= mac_io_port_dq_0_o @[TLSPI.scala 62:11]
    io_port_dq_0_oe <= mac_io_port_dq_0_oe @[TLSPI.scala 62:11]
    io_port_dq_1_o <= mac_io_port_dq_1_o @[TLSPI.scala 62:11]
    io_port_dq_1_oe <= mac_io_port_dq_1_oe @[TLSPI.scala 62:11]
    io_port_dq_2_o <= mac_io_port_dq_2_o @[TLSPI.scala 62:11]
    io_port_dq_2_oe <= mac_io_port_dq_2_oe @[TLSPI.scala 62:11]
    io_port_dq_3_o <= mac_io_port_dq_3_o @[TLSPI.scala 62:11]
    io_port_dq_3_oe <= mac_io_port_dq_3_oe @[TLSPI.scala 62:11]
    io_port_cs_0 <= mac_io_port_cs_0 @[TLSPI.scala 62:11]
    io_port_cs_1 <= mac_io_port_cs_1 @[TLSPI.scala 62:11]
    io_port_cs_2 <= mac_io_port_cs_2 @[TLSPI.scala 62:11]
    io_port_cs_3 <= mac_io_port_cs_3 @[TLSPI.scala 62:11]
    TLMonitor_reset <= reset
    TLMonitor_io_in_a_ready <= auto_r_in_d_ready @[RegisterRouter.scala 62:24]
    TLMonitor_io_in_a_valid <= auto_r_in_a_valid @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_opcode <= auto_r_in_a_bits_opcode @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_param <= auto_r_in_a_bits_param @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_size <= auto_r_in_a_bits_size @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_source <= auto_r_in_a_bits_source @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_address <= auto_r_in_a_bits_address @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_a_bits_mask <= auto_r_in_a_bits_mask @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_c_valid <= auto_r_in_c_valid @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_d_ready <= auto_r_in_d_ready @[LazyModule.scala 171:31 Nodes.scala 329:76]
    TLMonitor_io_in_d_valid <= auto_r_in_a_valid @[RegisterRouter.scala 62:24]
    TLMonitor_io_in_d_bits_opcode <= pad(_T_281, 3) @[Nodes.scala 329:76 RegisterRouter.scala 77:19]
    TLMonitor_io_in_d_bits_size <= bits(_T_283, 1, 0) @[RegisterRouter.scala 73:35]
    TLMonitor_io_in_d_bits_source <= bits(_T_283, 8, 2) @[RegisterRouter.scala 72:35]
    TLMonitor_io_in_e_valid <= auto_r_in_e_valid @[LazyModule.scala 171:31 Nodes.scala 329:76]
    fifo_reset <= reset
    fifo_io_ctrl_fmt_proto <= ctrl_fmt_proto @[TLSPI.scala 64:20]
    fifo_io_ctrl_fmt_endian <= ctrl_fmt_endian @[TLSPI.scala 64:20]
    fifo_io_ctrl_fmt_iodir <= ctrl_fmt_iodir @[TLSPI.scala 64:20]
    fifo_io_ctrl_fmt_len <= ctrl_fmt_len @[TLSPI.scala 64:20]
    fifo_io_ctrl_cs_mode <= ctrl_cs_mode @[TLSPI.scala 65:19]
    fifo_io_ctrl_wm_tx <= ctrl_wm_tx @[TLSPI.scala 66:19]
    fifo_io_ctrl_wm_rx <= ctrl_wm_rx @[TLSPI.scala 66:19]
    fifo_io_link_tx_ready <= mac_io_link_tx_ready @[TLSPI.scala 118:17]
    fifo_io_link_rx_valid <= mac_io_link_rx_valid @[TLSPI.scala 118:17]
    fifo_io_link_rx_bits <= mac_io_link_rx_bits @[TLSPI.scala 118:17]
    fifo_io_tx_valid <= and(_T_1428, _T_1435) @[RegMapFIFO.scala 18:30]
    fifo_io_tx_bits <= bits(auto_r_in_a_bits_data, 7, 0) @[RegisterRouter.scala 62:24]
    fifo_io_rx_ready <= and(_T_2242, _T_930) @[RegisterRouter.scala 62:24]
    mac_reset <= reset
    mac_io_port_dq_0_i <= io_port_dq_0_i @[TLSPI.scala 62:11]
    mac_io_port_dq_1_i <= io_port_dq_1_i @[TLSPI.scala 62:11]
    mac_io_port_dq_2_i <= io_port_dq_2_i @[TLSPI.scala 62:11]
    mac_io_port_dq_3_i <= io_port_dq_3_i @[TLSPI.scala 62:11]
    mac_io_ctrl_sck_div <= ctrl_sck_div @[TLSPI.scala 67:19]
    mac_io_ctrl_sck_pol <= ctrl_sck_pol @[TLSPI.scala 67:19]
    mac_io_ctrl_sck_pha <= ctrl_sck_pha @[TLSPI.scala 67:19]
    mac_io_ctrl_dla_cssck <= ctrl_dla_cssck @[TLSPI.scala 68:19]
    mac_io_ctrl_dla_sckcs <= ctrl_dla_sckcs @[TLSPI.scala 68:19]
    mac_io_ctrl_dla_intercs <= ctrl_dla_intercs @[TLSPI.scala 68:19]
    mac_io_ctrl_dla_interxfr <= ctrl_dla_interxfr @[TLSPI.scala 68:19]
    mac_io_ctrl_cs_id <= ctrl_cs_id @[TLSPI.scala 69:18]
    mac_io_ctrl_cs_dflt_0 <= ctrl_cs_dflt_0 @[TLSPI.scala 69:18]
    mac_io_ctrl_cs_dflt_1 <= ctrl_cs_dflt_1 @[TLSPI.scala 69:18]
    mac_io_ctrl_cs_dflt_2 <= ctrl_cs_dflt_2 @[TLSPI.scala 69:18]
    mac_io_ctrl_cs_dflt_3 <= ctrl_cs_dflt_3 @[TLSPI.scala 69:18]
    mac_io_link_tx_valid <= fifo_io_link_tx_valid @[TLSPI.scala 118:17]
    mac_io_link_tx_bits <= fifo_io_link_tx_bits @[TLSPI.scala 118:17]
    mac_io_link_cnt <= fifo_io_link_cnt @[TLSPI.scala 118:17]
    mac_io_link_fmt_proto <= fifo_io_link_fmt_proto @[TLSPI.scala 118:17]
    mac_io_link_fmt_endian <= fifo_io_link_fmt_endian @[TLSPI.scala 118:17]
    mac_io_link_fmt_iodir <= fifo_io_link_fmt_iodir @[TLSPI.scala 118:17]
    mac_io_link_cs_set <= fifo_io_link_cs_set @[TLSPI.scala 118:17]
    mac_io_link_cs_clear <= fifo_io_link_cs_clear @[TLSPI.scala 118:17]
    ctrl_fmt_proto <= mux(reset, UInt<2>("h0"), _GEN_14) @[TLSPI.scala 58:{17,17}]
    ctrl_fmt_endian <= mux(reset, UInt<1>("h0"), _GEN_15) @[TLSPI.scala 58:{17,17}]
    ctrl_fmt_iodir <= mux(reset, UInt<1>("h0"), _GEN_16) @[TLSPI.scala 58:{17,17}]
    ctrl_fmt_len <= mux(reset, UInt<4>("h8"), _GEN_17) @[TLSPI.scala 58:{17,17}]
    ctrl_sck_div <= mux(reset, UInt<12>("h3"), _GEN_0) @[TLSPI.scala 58:{17,17}]
    ctrl_sck_pol <= mux(reset, UInt<1>("h0"), _GEN_9) @[TLSPI.scala 58:{17,17}]
    ctrl_sck_pha <= mux(reset, UInt<1>("h0"), _GEN_8) @[TLSPI.scala 58:{17,17}]
    ctrl_cs_id <= mux(reset, UInt<2>("h0"), _GEN_20) @[TLSPI.scala 58:{17,17}]
    ctrl_cs_dflt_0 <= or(reset, _GEN_1) @[TLSPI.scala 58:{17,17}]
    ctrl_cs_dflt_1 <= or(reset, _GEN_2) @[TLSPI.scala 58:{17,17}]
    ctrl_cs_dflt_2 <= or(reset, _GEN_3) @[TLSPI.scala 58:{17,17}]
    ctrl_cs_dflt_3 <= or(reset, _GEN_4) @[TLSPI.scala 58:{17,17}]
    ctrl_cs_mode <= mux(reset, UInt<2>("h0"), _GEN_10) @[TLSPI.scala 58:{17,17}]
    ctrl_dla_cssck <= mux(reset, UInt<8>("h1"), _GEN_5) @[TLSPI.scala 58:{17,17}]
    ctrl_dla_sckcs <= mux(reset, UInt<8>("h1"), _GEN_6) @[TLSPI.scala 58:{17,17}]
    ctrl_dla_intercs <= mux(reset, UInt<8>("h1"), _GEN_18) @[TLSPI.scala 58:{17,17}]
    ctrl_dla_interxfr <= mux(reset, UInt<8>("h0"), _GEN_19) @[TLSPI.scala 58:{17,17}]
    ctrl_wm_tx <= mux(reset, UInt<4>("h0"), _GEN_7) @[TLSPI.scala 58:{17,17}]
    ctrl_wm_rx <= mux(reset, UInt<4>("h0"), _GEN_13) @[TLSPI.scala 58:{17,17}]
    ie_txwm <= mux(reset, UInt<1>("h0"), _GEN_11) @[TLSPI.scala 71:{15,15}]
    ie_rxwm <= mux(reset, UInt<1>("h0"), _GEN_12) @[TLSPI.scala 71:{15,15}]
